Service Manuals, User Guides, Schematic Diagrams or docs for : apple Apple Powerbook G4 A1139_MLB_PB17_051-6839_RevE
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8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
E 408395 PRODUCTION RELEASED 11/02/05 ?
D D
PDF
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CSA CONTENTS SYNC MASTER DATE PDF
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CSA CONTENTS SYNC MASTER DATE
1 1 Table Of Contents N/A N/A 41 52 DDR2 SO-DIMM Slot B MARIAS-MDIFF N/A
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2 2 Board Information N/A N/A 42 55 M11 Frame Buffer Constraints MARIAS 08/24/2005
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3 3 System Block Diagram MARIAS 08/24/2005 43 56 I2 AGP Interface MARIAS 08/24/2005
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4 4 Power Block Diagram MARIAS 08/24/2005 44 57 GPU (M11) AGP Interface MARIAS 08/24/2005
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5 5 Revision History N/A N/A 45 58 GPU VCore Supply MARIAS 08/24/2005
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6 6 Q41C Pin Swaps N/A N/A 46 59 GPU (M11) Core Power MARIAS 08/24/2005
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7 7 Functional Test Points MARIAS 08/24/2005 47 60 GPU (M11) I/O Power MARIAS 08/24/2005
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8 8 I2C Connections MARIAS 08/24/2005 48 61 GPU (M11) Frame Buffer I/F MARIAS 08/24/2005
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9 9 JTAG Connections MARIAS 08/24/2005 49 62 GPU Frame Buffer A MARIAS 08/24/2005
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10 10 Power Synonyms MARIAS 08/24/2005 50 63 GPU Frame Buffer B MARIAS 08/24/2005
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11 11 Signal Synonyms MARIAS 08/24/2005 51 64 GPU (M11) GPIOs/Straps MARIAS 08/24/2005
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12 12 Power Inputs MARIAS 08/24/2005 52 65 GPU (M11) Clocks/Misc MARIAS 08/24/2005
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13 13 Battery Charger MARIAS 08/24/2005 53 66 GPU (M11) DVI/DAC Outputs MARIAS 08/24/2005
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14 14 12.8V PBUS/PMU Supplies MARIAS 08/24/2005 54 67 Lower TMDS Transmitter MARIAS 08/24/2005
C
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15
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15 5V/3.3V Supplies MARIAS 08/24/2005
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55
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68 Upper TMDS Transmitter MARIAS 08/24/2005 C
16 16 1.8V/1.5V Supplies MARIAS 08/24/2005 56 69 Internal Display Conns MARIAS 08/24/2005
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17 17 2.5V Supply MARIAS 08/24/2005 57 70 External Display Conns MARIAS-PDIFF 06/02/2005
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18 19 Vesta Power & Misc MARIAS 08/24/2005 58 71 BootROM MARIAS 08/24/2005
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19 21 I2 Power MARIAS 08/24/2005 59 72 I2 PCI Interface MARIAS 08/24/2005
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20 22 I2 Power Supplies MARIAS 08/24/2005 60 73 Q85 AIRPORT/BT CONN MARIAS-MDIFF N/A
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21 23 I2 Supplemental MARIAS 08/24/2005 61 74 Cardbus MARIAS 08/24/2005
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22 24 I2 Miscellaneous MARIAS 08/24/2005 62 75 NEC USB2 MARIAS 08/24/2005
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23 25 PCI Clock Buffer MARIAS 08/24/2005 63 81 I2 UATA Interface MARIAS 08/24/2005
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24 26 LEDs/Reset/Debug MARIAS 08/24/2005 64 82 HDD/ODD Connectors MARIAS-PDIFF 06/02/2005
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25 27 Power Management Unit (PMU05) MARIAS 08/24/2005 65 84 I2 Ethernet Interface MARIAS 08/24/2005
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26 29 Power Sequencing MARIAS 08/24/2005 66 85 Vesta Ethernet PHY MARIAS 08/24/2005
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27 30 Fan Controller MARIAS 08/24/2005 67 86 Ethernet Connector N/A N/A
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28 31 ALS Support MARIAS 08/24/2005 68 88 I2 FireWire Interface MARIAS 08/24/2005
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29 32 Sudden Motion Sensor MARIAS 08/24/2005 69 89 Vesta FireWire PHY MARIAS 08/24/2005
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30 33 Q41C Internal I/O I N/A N/A 70 90 FireWire Ports MARIAS-PDIFF 06/02/2005
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31 34 Q41C Internal I/O II N/A N/A 71 91 FireWire Series Term MARIAS 08/24/2005
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32 35 I2 Processor Interface MARIAS 08/24/2005 72 92 I2 USB Interface MARIAS 08/24/2005
B TABLE_TABLEOFCONTENTS_ITEM
33 36 A8 MaxBus (CPU0) MARIAS 08/24/2005
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73 93 NEC USB2 Interface MARIAS 08/24/2005
B
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34 37 A8 Configuration Straps MARIAS 08/24/2005 74 100 Audio Board Connector N/A N/A
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35 38 A8 Power (CPU0) MARIAS 08/24/2005 75 110 Spacing & Physical Constraints MARIAS 08/24/2005
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36 39 CPU VCore Supply MARIAS 08/24/2005 76 111 Spacing & Physical Constraints 2 MARIAS 08/24/2005
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37 46 CPU AVDD Supply MARIAS 08/24/2005 77 112 Cross Reference Page
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38 47 I2 Memory Interface MARIAS 08/24/2005 78 113 Cross Reference Page
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39 48 Memory Series Termination MARIAS-NDIFF N/A 79 114 Cross Reference Page
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40 50 DDR2 SO-DIMM Slot A MARIAS-MDIFF N/A 80 115 Cross Reference Page
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DIMENSIONS ARE IN MILLIMETERS
METRIC Apple Computer Inc.
XX
A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
TABLE_5_HEAD
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION AGREES TO THE FOLLOWING
ENG APPD MFG APPD
TABLE_5_ITEM
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
051-6839 1 SCHEM,BOZEMAN,Q41C SCH1 ANGLES II NOT TO REPRODUCE OR COPY IT
TABLE_5_ITEM
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
820-1810 1 PCBF,BOZEMAN,Q41C PCB1 CRITICAL QA APPD DESIGNER TITLE
TABLE_5_ITEM
DO NOT SCALE DRAWING
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:SYV] CRITICAL EEE_SYV
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:TML] CRITICAL EEE_TML
TABLE_5_ITEM
RELEASE SCALE SCHEM,MLB,PB17"
TABLE_5_ITEM
NONE
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:USH] CRITICAL EEE_USH
SIZE DRAWING NUMBER REV.
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:USJ] CRITICAL EEE_USJ
TABLE_5_ITEM
MATERIAL/FINISH
NOTED AS D 051-6839 E
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Design-Specific Rules
TABLE_SPACING_RULE
CHASSIS GND CONNECTIONS BOARD HOLES
TABLE_SPACING_RULE
STANDARD =DEFAULT * =DEFAULT =DEFAULT =DEFAULT =DEFAULT =DEFAULT GND_CHASSIS_UPPER_DVI
=GND_CHASSIS_DVI_HOLE
CHASSIS MOUNTS
TABLE_SPACING_RULE
BGA_P1MM 10 * 0.10 MM 1.25 MM 0.1 MM 12.5 MM 15.0 MM
MAKE_BASE=TRUE
VOLTAGE=0V =GND_CHASSIS_DVI2
2
HEATSINK MOUNTS INVERTER
TABLE_SPACING_RULE MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_DVI3
57
57
MECH. HOLES
BGA_P2MM 20 * 0.20 MM 1.25 MM 0.1 MM 12.5 MM 15.0 MM ZT0210
TABLE_SPACING_RULE GND_CHASSIS_FW_LOWER_DVI
=GND_CHASSIS_FW_HOLE 255R158
DEFAULT * 0.1 MM 2.5 MM 0.15 MM 10.0 MM 15.0 MM MAKE_BASE=TRUE
=GND_CHASSIS_DVI1
2
1
ZT0230 1
TABLE_SPACING_ASSIGNMENT
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
57 MCO HOLE B 146R126 SH0200
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_DVI4 57 1 2 OG-503040
SHLD-SM-LF
TABLE_SPACING_ASSIGNMENT "1MM" area defined around BGAs to =GND_CHASSIS_TV 57
D *
TABLE_SPACING_ASSIGNMENT
* 1MM BGA_P1MM reduce DRCs caused by fan-out. =GND_CHASSIS_ENET 67 ZT0204
255R158
3
D
=GND_CHASSIS_FW_PORT1 70 =GND_CHASSIS_DVI_HOLE 2
AGP_STB * 1MM BGA_P2MM 1 MCO HOLE F
TABLE_SPACING_ASSIGNMENT "BGA_P2MM" rule ensures these critical =GND_CHASSIS_FW_PORT2 70
CLOCK * 1MM BGA_P2MM signals do not fan-out routed next =GND_CHASSIS_FW_EMI 70 =GND_CHASSIS_INV_GND_CLIP
TABLE_SPACING_ASSIGNMENT
to any other signals. =GND_CHASSIS_SVIDEO_HOLE 2 ZT0205
RAM_DIFF * 1MM BGA_P2MM
GND_CHASSIS_LCD
235R126 MCO HOLE G
=GND_CHASSIS_LCD1 56 1
TABLE_PHYSICAL_RULE MAKE_BASE=TRUE
VOLTAGE=0V =GND_CHASSIS_LCD2
BS0200 ZT0220
MIN_LINE_WIDTH=0.6 mm
56
STDOFF-217ODX150IDX35H-TH-LF 146R126
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_LCD3
TABLE_PHYSICAL_RULE
=GND_CHASSIS_LCD4
56
ZT0203 1 1
STANDARD
TABLE_PHYSICAL_RULE
* =DEFAULT =DEFAULT =DEFAULT =DEFAULT 56 235R126 MCO HOLE K
GND_CHASSIS_INVERTER 1
DEFAULT * Y 0.100 MM 0.100 mm 1.25 MM =GND_CHASSIS_INV_GND_CLIP 2
MAKE_BASE=TRUE =GND_CHASSIS_SVIDEO_HOLE 2 =GND_CHASSIS_FW_HOLE 2
VOLTAGE=0V =GND_CHASSIS_INVERTER1 56
MIN_LINE_WIDTH=0.6 mm
Layer-specific rules for 90-ohm differential impedance MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_INVERTER2 56
TABLE_SPACING_RULE
TABLE_SPACING_RULE
SPEAKER CLIPS
90_OHM_DIFF
TABLE_SPACING_RULE
TOP,BOTTOM 2.5 MM 0.200 MM 2.5 MM 1.0 MM PCB MOUNTS SP0201 SP0202 SP0203
90_OHM_DIFF * 2.5 MM 0.200 MM 2.5 MM 1.0 MM SPKR_CLIP_P84-LF SPKR_CLIP_P84-LF SPKR_CLIP_P84-LF
ZT0201
TABLE_PHYSICAL_RULE 235R126 MCO HOLE E 1 1 1
1
TABLE_PHYSICAL_RULE
90_OHM_DIFF TOP,BOTTOM Y 0.118 MM 0.1 MM 5 MM
TABLE_PHYSICAL_RULE
ZT0202
90_OHM_DIFF * Y 0.125 MM 0.1 MM 5 MM 235R126 MCO HOLE H SP0204 SP0205 SP0206
1 SPKR_CLIP_P84-LF SPKR_CLIP_P84-LF SPKR_CLIP_P84-LF
Layer-specific rules for 100-ohm differential impedance Layer-specific rules for 60-ohm single-ended impedance
TABLE_SPACING_RULE TABLE_PHYSICAL_RULE 1 1 1
C TABLE_SPACING_RULE
100_OHM_DIFF
TABLE_SPACING_RULE
TOP,BOTTOM 2.5 MM 0.200 MM 2.5 MM 1.0 MM
TABLE_PHYSICAL_RULE
60_OHM_SE * Y 0.076 MM =50_OHM_SE =50_OHM_SE
C
100_OHM_DIFF * 2.5 MM 0.200 MM 2.5 MM 1.0 MM
Layer-specific rules for 50-ohm single-ended impedance
TABLE_SPACING_RULE
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
50_OHM_SE * 2.5 MM 0.125 MM 2.5 MM 1.0 MM
BOARD STACK-UP AND CONSTRUCTION
100_OHM_DIFF TOP,BOTTOM Y 0.092 MM 0.1 MM 5 MM
TABLE_PHYSICAL_RULE TABLE_PHYSICAL_RULE SEE BOARD FILE FOR DETAILED INFORMATION
100_OHM_DIFF * Y 0.100 MM 0.1 MM 5 MM CONVENTIONAL CONSTRUCTION WITH Pxx TH VIA
TABLE_PHYSICAL_RULE
50_OHM_SE * Y 0.100 MM 0.100 MM 1.25 MM
Layer-specific rules for 110-ohm differential impedance SIGNAL (1/2 OZ + COPPER PLATING)
TABLE_SPACING_RULE
1
TABLE_SPACING_RULE PREPREG GROUND (1/2 OZ)
110_OHM_DIFF
TABLE_SPACING_RULE
TOP,BOTTOM 2.5 MM 0.330 MM 2.5 MM 1.0 MM 2 CORE
110_OHM_DIFF * 2.5 MM 0.300 MM 2.5 MM 1.0 MM SIGNAL (1/2 OZ)
TABLE_PHYSICAL_RULE
TMDS RETURN CURRENT VIAS 3
PREPREG SIGNAL (1/2 OZ)
TABLE_PHYSICAL_RULE ZT0250
HOLE-VIA-P5RP25
ZT0254
HOLE-VIA-P5RP25
4
110_OHM_DIFF
TABLE_PHYSICAL_RULE
TOP,BOTTOM Y 0.080 MM 0.1 MM 5 MM 1 1
CORE GROUND (1/2 OZ)
110_OHM_DIFF * Y 0.085 MM 0.1 MM 5 MM 5
ZT0251 ZT0255 PREPREG CUT POWER PLANE (1 OZ)
Portable-specific Override Rules
TABLE_SPACING_RULE
HOLE-VIA-P5RP25
1
HOLE-VIA-P5RP25
1
6
CORE CUT POWER PLANE (1 OZ)
TABLE_SPACING_RULE
AGP 201 * 0.2 MM
ZT0252
HOLE-VIA-P5RP25
ZT0256
HOLE-VIA-P5RP25
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