Service Manuals, User Guides, Schematic Diagrams or docs for : Medion wim2220 md96970 ec4da_WISTRON_ME3
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5 4 3 2 1
ME3 Block Diagram Intel CPU Project code : 91.4X601.001
SYSTEM DC/DC
TPS51120
Meron 2M/4M SV PCB P/N : INPUTS OUTPUTS
FSB:667 or 800 MHz
CLK GEN 4,5,6
Revision : DCBATOUT
5V_S3
3V_S5
D
G792 REALTEK RTM875 SYSTEM DC/DC D
22 3 Host BUS MAX8743
533/667MHz
INPUTS OUTPUTS
TV OUT 15 1D05V_S0
DDRII DCBATOUT
DDRII 667 Channel A Crestline-GM/GML 1D8V_S3
Slot 0 13,14
AGTL+ CPU I/F DDR I/F
nVIDIA CRT 15
DDRII INTEGRATED GRAHPICS SYSTEM DC/DC
DDRII 667 Channel B NB8M-GS FAN5234
LVDS, CRT I/F PCIE x 16
Slot 1 13,14 7,8,9,10,11,12 44,45,46 LCD 16 INPUTS OUTPUTS
VGA_CORE_S0
DCBATOUT
11A
DMI I/F HDMI 17
100MHz MAXIM CHARGER
Power Switch New card EEPROM MAX8725
PCI-E x 1 46
G577 23 INPUTS OUTPUTS
C 23 GDDR3 BT+
C
Mini Card_2 Mini Card_1 INTEL Graphics RAM DCBATOUT 18V 3.0A
Robson 802.11a/b/g/n 23 PCI-E x 2
23 5V 100mA
ICH8-M 256-Mbit
47,48
RJ45 10/100 Controller PCI-E x 1 10 USB 2.0/1.1 ports CPU DC/DC
CONN 25 Realtek ETHERNET (10/100/1000Mb) MAX8736ETL
RTL8101E 24 High Definition Audio Finger print 26 INPUTS OUTPUTS
ATA 66/100
Mic In Codec VCC_CORE
ALC662 ACPI 1.1 DCBATOUT
AZALIA Camera 26 0.844~1.3V
LPC I/F 44A
Line In 34
PCI/PCI BRIDGE or
27MHz
RF 26 Blue tooth 26
B PCB LAYER B
AMP 32.768KHz
INT.SPKR G1432 L1: Signal 1
35 USB X 4 28
L2: GND
L3: Signal 2
Line Out AMP L4: Signal 3
Realtek MS/MS Pro/xD/
(SPDIF) G1412 USB 2.0
35
RTL5158 27 MMC/SD 4 in 1 27 L5: GND
L6: VCC
L7: Signal 4
MODEM L8: Signal 5
RJ11 MDC Card AZALIA 18,19,20,21 LPC BUS LPC L9: GND
DEBUG L10: Signal 5
28
INT. MIC Array CONN. 32
Digital KBC 32.768KHz TPM Prepare by Steven CF Chou
A
Codec Winbond SLB9635TT A
ALC268 SPI
HDMI WPC8763 Wistron Corporation
(SPDIF) 31 32 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SATA SATA PATA Taipei Hsien 221, Taiwan, R.O.C.
Title
E-SATA E-SATA CAPACITY Touch INT. Flash Rom
32.768KHz
Block Diagram
CONN SIL3531 HDD30 CDROM BUTTON 33 Pad W25X80-VSS Size Document Number Rev
28 29 30 33
KB 33 32
A3
ME3-Discrete SA
Date: Monday, July 30, 2007 Sheet 1 of 51
5 4 3 2 1
A B C D E
INTEL ICH8-M STRAP PIN
U45 : 71.0NB8M.00U (VGA)
U35: 71.00662.00G (Audio)
U28: 71.08763.B0G (KBC)
XOR Chain Entrance Strap U74: 71.08101.B0G (LAN)
Signal Usage/When Sampled Comment U26: 71.ICH8M.C0U (SB)
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 ICH_RSVD
tp3 AZ_DOUT_ICH Description U18: 71.PM965.A0U (NB)
RSVD TV1: 22.10021.H21
PCIE Port Config 1 bit1, pulled low at rising edge of PWROK.When TP3 not 0 0 Hole,Spring
4 Rising Edge of PWROK pulled low at rising edge of PWROK,sets bit1 of 0
1
1
0
Enter XOR Chain
Normal Operation(default) HDMI1: 22.10296.011 4
RPC.PC(Config Registers:offset 224h) 1 1 Set PCIE port cofig bit1
HDA_SYNC PCIE Port Config 1 bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
GNT2# PCIE Port Config 2 bit0, Sets bit2 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
GPIO20 Reserved Weak Internal PULL-DOWN.NOTE:This signal should
not be pull HIGH.
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
GNT3# Top-Block Swap Override. cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the PCI_GNT#3 low = A16 swap override enable
Top-Swap bit until the system is rebooted high = default
without GNT3# being pulled down. BOOT BIOS Strap
PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
GNT0# Boot BIOS Destination Controllable via Boot BIOS Destination bit
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). 0 1 SPI
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 0 PCI
1 1 LPC(Default)
Integrated VccSus1_05
VccSus1_5 and VccCL1_5 Enables integrated VccSus1_05,VccSus1_5 and integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN VRM Enable/Disable.Always VccCL1_5 VRM when sampled high
SM_INTVRMEN High=Enable Low=Disable
sampled.
3 Integrated VccLAN1_05 Enables integrated VccLAN1_05,VccCL1_05 VRM
integrated VccLan1_05VccCL1_05 3
LAN100_SLP VccCL1_05 VRM enable when sampled high LAN100_SLP High=Enable Low=Disable
/Disable. Always sampled.
SATALED# PCIE LAN REVERSAL.Rising This signal has weak internal pull-up. DEFAULE HIGH
Edge of PWROK. set bit27 of MPC.LR(Device28:Function0:Offset D8)
If sampled high, the system is strapped to the No Reboot Strap
SPKR No Reboot. "No Reboot" mode(ICH8M will disable the TCO Timer SPKR LOW = Defaule
Rising Edge of PWROK. system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot
TP3 XOR Chain Entrance. This signal should not be pull low unless using
Rising Edge of PWROK. XOR Chain testing.
GPIO33/
Internal Pull-Up.If sampled low,the Flash Descriptor
Flash Descriptor Security Security will be overidden.if high,the Security
INTEL ICH8-M INTEGRATED
HDA_DOCK_EN# Override Strap
Rising Edge of PWROK.
measures defined in the Flash Descriptor will be in
effect.
This should only be used in manufacturing
8.2K PULL HIGH PULL-UPS and PULL-DOWNS
environments
SIGNAL Resistor Type/Value
HDA_BIT_CLK PULL-DOWN 20K
HDA_RST# NONE
2 HDA_SDIN[3:0] PULL-DOWN 20K 2
HDA_SDOUT PULL-DOWN 20K
HDA_SYNC PULL-DOWN 20K
INTEL CRESTLINE STRAP PIN MB: 07230
LED: 07537 GNT[3:0] PULL-UP 20K
CFG Strap LOW 0 HIGH 1 FP: 07546 GPIO[20] PULL-DOWN 20K
CFG 5 Audio: 07545 LDA[3:0]#/FHW[3:0]# PULL-UP 20K
DMI X 2 DMI X 4 USB: 07547
CFG 8 LAN_RXD[2:0] PULL-UP 20K
Low Power PCI Express Normal Low Power mode
CFG 9 LDRQ[0] PULL-UP 20K
PCI Express Graphics Lane Reversal Normal Mode(Lanes
Lane Reversal number in order) LDRQ[1]/GPIO23 PULL-UP 20K
CFG 16
FSB Dynamic ODT Disabled Enabled PME# PULL-UP 20K
CFG 19
DMI Lane Reserved Normal Operation Reserved Lane PWRBTN# PULL-UP 20K
CFG 20 Only PCIE or SDVO PCIE and SDVO are
Concurrent SDVO/PCIE is operation operation simultaneous SATALED# PULL-UP 20K
SDVO_CTRL_DATA NO SDVO Card SDVO Card Present SPI_CS1# PULL-UP 20K
Present
SDVO Present SPI_CLK PULL-UP 20K
CFG 12 XOR/ALL-Z SPI_MOSI PULL-UP 20K
1 CFG 13
LL(00) Reserved
1
SPI_MISO PULL-UP 20K
LH(01) XOR Mode Enabled Wistron Corporation
HL(10) All Z Mode Enabled TACH_[3:0] PULL-UP 20K 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
HH(11) Normal Operation Taipei Hsien 221, Taiwan, R.O.C.
SPKR PULL-DOWN 20K
Title
TP[3] PULL-UP 20K
Table of Content
USB[9:0][P,N] PULL-DOWN 15K Size Document Number Rev
A3
CL_RST# TBD ME3-Discrete
Date: Friday, September 14, 2007 Sheet 2 of 51
A B C D E
3D3V_S0 5 3D3V_S0_CK505 4 3 2 1
L15
1 2
MLB-160808-18-GP DY DY 3D3V_S0_CK505 1D25V_S0_CK505_IO
1
1
1
1
1
1
1
1
C343 C330 C603 C596 C598 C618 C597 C599
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
X2
CLK_XTAL_IN 1 2 CLK_XTAL_OUT
X-14D31818M-36GP
1
1
D C321 C322
D
SC33P50V2JN-3GP SC33P50V2JN-3GP
2
2
16
46
62
23
19
27
43
52
33
56
4
9
U24
3D3V_S0
VDD_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_CPU_IO
VDD_REF
VDD_48
VDD_SRC
VDD_CPU
VDD_PLL3
VDD_PLL3_IO
VDD_PCI
1 R354 2
61 CPU_BCLK 1 4 SRN0J-6-GP CLK_CPU_BCLK 4
1D25V_S0 0R3-0-U-GP 1D25V_S0_CK505_IO CPU-0 CPU_BCLK#
CPU-0# 60 2 3 CLK_CPU_BCLK# 4
RN29
L18 DY CLK_XTAL_IN MCH_BCLK
3 XIN CPU-1 58 1 4 SRN0J-6-GP CLK_MCH_BCLK 7
1 2 C607 SC4D7P50V2CN-1GP CLK_XTAL_OUT 2 57 MCH_BCLK# 2 3 CLK_MCH_BCLK# 7
XOUT CPU-1# RN32
MLB-160808-18-GP DY 1 2 54 CPU_XDP 1 4 SRN0J-6-GP CLK_PCIE_ESATA 29
SRC-8/CPU_ITP
1
1
1
1
1
1
1
1
C300 C341 C601 C610 C605 C611 C619 C337 53 CPU_XDP# 2 3 CLK_PCIE_ESATA# 29
FSA SRC-8#/CPU_ITP# RN36
20 CLK_48M_ICH 1 2 17 FSLA/USB48
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
2
2
2
2
2
2
2
2
R338 33R2J-2-GP 51 PCIE_LAN 1 4 SRN0J-6-GP CLK_PCIE_LAN 24
SRC-7/CR#_F PCIE_LAN#
SRC-7#/CR#_E 50 2 3 CLK_PCIE_LAN# 24
45 RN39
20 H_STP_PCI# PCI_STOP#/SRC-5 PCIE_MINI1
20 H_STP_CPU# 44 CPU_STOP#/SRC-5# SRC-6 48 1 4 SRN0J-6-GP CLK_PCIE_MINI1 23
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