Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6390
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8 7 6 5 4 3 2 1
D
MS-6390 Ver:30B Cover Sheet 1 D
Block Diagram 2
VIA KM266 + VT8235 Chipset CLOCK GEN 3
AMD CPU Sockets 462 4-5
Via VT8375 KM266 North Bridge 6-8
DDR SLOT 9
CPU: DDR TERMINATOR 10
AMD Athlon XP / Athlon / Duron Socket 462 Processor Via VT8235 South Bridge 11 - 13
AGP SLOT 14
System Chipset:
PCI SLOTS 15 - 16
C
VIA VT8375 (KM266 ) + VT8325 CD C
LAN 17
On Board Chipset: IDE CONNECTOR 18
LPC Super I/O -- W83697HF USB CONNECTOR 19
Lan : Via PHY VT6103 KB/MS CONNECTOR 20
AC'97 CODEC 21
Expansion Slots:
AUDIO CONNECTOR 22
AGP 3.0 Slot * 1
FLASH ROM & Battery 23
DDR Slot * 2
PCI 2.2 Slot * 3 LPC I/O(W83697HF) 24
CNR Slot * 1 HARDWARE MONITOR 25
B
PARALLEL PORT & SERIAL PORTS 26 B
SERIAL BUFFER & WOL & WOR 27
VRM 9.X 28
ACPI Controller & Regulators 29
ATX POWER CON & HARDWARE MONITOR & VGA CON 30
FRONT PANEL 31
Decoupling Capacitor 32
A A
MICRO-STAR INT'L CO.,LTD.
Title
COVER PAGE
Size Document Number Rev
C MS-6390 30B
Date: Tuesday, December 10, 2002 Sheet 1 of 32
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
System Block Diagram
APICCPU (14.318MHz) + 12V
D (100/133MHz) PCI CLK (33MHz) - 12V D
SOCKET-462 Host CLK
Clock Gen. APICSB (14.318MHz) + 5V
ATX Conn.
AGP CLK (66MHz) - 5V
3.3V
NBVLINK(66MHz)
Host Bus VCC5SBY
(200/266MHz) SBVLINK(66MHz)
Support Dual Monitor
Mem. CLK
GCLK14(14.318MHz) SSTL-2 Termination
VGA VGA Connector
D-SUB DDR SDRAM
(200/266MHz) VCC5SBY
Via VT8375 VCC3
VCC3SBY VCCM
4X (66MHz) AGP
AGP Connector AGP CONNECTOR VGA
DIMM 1 DIMM 2 Rtt
C VCC25SBY C
V-Link
( 66MHz X 4 )
DDR_VTT
AC'97
Audio Codec
PCI SLOT 3 PCI SLOT 2 PCI SLOT 1 Analog In
VCC2_5
Via VT8235 Analog Out
IDE 1 IDE 2
KEYBOARD PS/2 (48MHz) VDDQ
/MOUSE
(33MHz)
USB 0 USB 2 USB 4
B Lan VCCA_PLL B
USB 1 USB 3 USB 5
LPC Bus
FAN FAN FAN CONTROL VOLTAGE MONITOR
1 2 VCC5SBY
5VDUAL KBUVCC
TEMPERATURE MONITOR VCC5
LPC Super I/O
Legacy FAN CONTROL
ROM
VCORE
GPIOs SERIAL PARALLEL FLOPPY
A A
MICRO-STAR INT'L CO.,LTD.
Title
System Block Diagram
Size Document Number Rev
CustomMS-6390 30B
Date: Tuesday, December 10, 2002 Sheet 2 of 32
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
By-Pass Capacitors
Place near to the Clock Outputs
Main Clock Generator Damping Resistors
Place near to the
Clock Outputs
D U2 D
VCC3 CY28341-2 A/ICS 950902 RN109 22-8p4r AGPCLK0 C221 10p
CP1 7 8 CPUCLK1
CPUCLK1 {6} VLCLK
5 48 5 6 CPUCLK-1 C222 10p
VDDAGP CPUCLK_PPT CPUCLK-1 {6}
16 49 3 4 CPUCLK0
VDDPCI CPUCLK_PPC CPUCLK-0 CPUCLK0 {4} AGPCLK1
X_COPPER 22 1 2 C223 X_10p
VDD48M CPUCLK-0 {4}
51 VDDCPU CPUCLKST 53
X_80-0805 CB3 CB4 CB5 CB6 CB7 55 52
L51 VDDREF CPUCLKSC
C605 22-8P4R 1 2 RN106 DDRCLK0 PCICLK1 C595 10p
CE1 0.1u 0.1u 0.1u 0.1u 0.1u 2 44 3 4 DDRCLK-0
GND2 DDRT0 DDRCLK1
9 GND9 DDRC0 43 5 6
10u/16V ECSMD 0.1u 13 42 7 8 DDRCLK-1 CN2 10p-8p4c
GND13 DDRT1 PCLKSB
19 GND48M DDRC1 41 1 2
33 38 22-8P4R 1 2 RN107 DDRCLK2 SIOPCLK 3 4
GND33 DDRT2 DDRCLK-2 PCICLK3
39 GND39 DDRC2 37 3 4 5 6
47 36 5 6 DDRCLK3 PCICLK2 7 8
GNDI DDRT3 DDRCLK-3
54 GND54 DDRC3 35 7 8
VCC3 32
L1 DDRT4 22-8P4R 1
DDRC4 31 2 RN108 DDRCLK4 APICCPU C224 X_10p
23 30 3 4 DDRCLK-4
X_80-0805 AVDD DDRT5 DDRCLK5 APICSB C225 X_10p
DDRC5 29 5 6
CP13 24 7 8 DDRCLK-5
CB8 CB9 AGND GCLK14 C226 X_10p
45
C BUFFER_IN C
X_COPPER 0.1u 1u 50 46 SBCLK14 C227 X_10p
VDDI FBOUT DCLKO {7}
R61 22 DCLKI {7}
VCC2_5 VCC2_5
6 MODE R62 22 USBCLK C228 X_10p
AGP0/MODE SELCPU AGPCLK0 {8}
34 7 R63 22
VDD3.3/2.5-34 AGP1/SEL_CPU VLCLK {11}
CB10 X_80-0805 CB11 CB12 8 R64 22 SIO48M C229 X_10p
AGP2/PCI_STOP# AGPCLK1 {14}
L2 40 VDD3.3/2.5-40
CP14
0.1u 1u 1u 10 FS1 R615 22
PCICLK_F/FS1 SELDDR# PCICLK1 {15}
PCICLK0/SEL_SD_DDR# 11
X_COPPER 12 MULTSEL0 RN11 22-8p4r
PCICLK1/MULTSEL0 By-Pass Capacitors
PCICLK2 14 7 8 PCICLK2 {16}
15 5 6 Place near to the Clock Buffer
PCICLK3 PCICLK3 {16}
{9,12,29} SMBCLK 27 SCLK PCICLK4 17 3 4 SIOPCLK {24}
28 18 1 2 CN21 X_10p-8p4c
{9,12,29} SMBDAT SDATA PCICLK5/CPU_STP# PCLKSB {11}
DDRCLK0 1 2
DDRCLK-0 3 4
R656 0 26 20 FS3 DDRCLK1 5 6
{29,31} FP_RST# RESET/PD# 48M/FS3 FS2
21 DDRCLK-1 7 8
24_48M/FS2 R66 22 USBCLK {13}
R67 22 SIO48M {24}
25 1 FS0 CN22 X_10p-8p4c
IREF REF0/FS0 R70 DDRCLK2
33 SBCLK14 {12} 1 2
B R69
VTT_PWRGD#/REF1 56 R72 22 APICSB {11}
DDRCLK-2
DDRCLK3
3 4 B
5 6
XOUT
475ST R73 X_22 DDRCLK-3 7 8
GCLK14 {8}
XIN
R75 10 APICCPU {4}
R673 X_330 CN23 X_10p-8p4c
VCC2_5
DDRCLK4
3
4
1 2
DDRCLK-4 3 4
VCC3 Y1 DDRCLK5 5 6
DDRCLK-5 7 8
FS1 X_2.7K R68
{12} FS1
14M-32pf-HC49S-D
CN24 10p-8p4c
FS0 R657 1K C241 C242 MULTSEL0 R77 X_0 CPUCLK0
22p 22p 1 2
CPUCLK-0 3 4
FS0 X_2.7K R76 CPUCLK-1 5 6
SELCPU R78 4.7K CPUCLK1 7 8
FS2 X_2.7K R74
VCC3 APICCPU 137ST R465
SELDDR# R658 X_4.7K
5
FS0 1
A 2
4 R682 22 GCLK14
A
U37 MICRO-STAR INT'L CO.,LTD.
NC7WZ08
3
DDRCLK[0:5] Title
DDRCLK[0:5] {9}
CLOCK GEN
DDRCLK-[0:5]
DDRCLK-[0:5] {9}
Size Document Number Rev
B MS-6390 30B
Date: Tuesday, December 10, 2002 Sheet 3 of 32
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCORE VCC3
R20 R21
CPU1A 680 1K
SDATA#0 AA35 AE1
{6} SDATA#[0:63] SDATA#1 SDATA0 A20M FERR A20M# {11} VCORE
W37 SDATA1 FERR AG1 FERR# {11}
SDATA#2 W35 AJ3
SDATA#3 SDATA2 INIT CPUINIT# {11}
Y35 SDATA3 INTR AL1 INTR {11} C
SDATA#4 U35 AJ1 FERR B Q15 TRST# 510 R18
D SDATA#5 SDATA4 IGNNE IGNNE# {11} NPN-3904LT1-S-SOT23 PLLTEST# 510 R19 D
U33 SDATA5 NMI AN3 NMI {11} E
SDATA#6 S37 AG3
SDATA#7 SDATA6 RESET CPURST# {29}
S33 SDATA7 SMI AN5 SMI# {11}
SDATA#8 STPCLK# RN3
AA33 SDATA8 STPCLK AC1 STPCLK# {11}
SDATA#9 AE37 DBREQ# 1 2
SDATA#10 SDATA9 TCK
AC33 SDATA10 PWROK AE3 PWRGD_CPU {29} 3 4
SDATA#11 AC37 TMS 5 6
SDATA#12 SDATA11 VCORE TDI
Y37 SDATA12 7 8
SDATA#13 AA37 N1
SDATA#14 SDATA13 PICCLK APICCPU {3}
AC35 N3 510-8p4r
SDATA#15 SDATA14 PICD0/BYPASSCLK APICD0 {11}
S35 SDATA15 PICD1/BYPASSCLK N5 APICD1 {11}
SDATA#16 Q37 R23
SDATA#17 SDATA16 COREFB- R22 C215 RN4
SDATA#18
Q35 SDATA17 COREFB- AG13
COREFB+
Near socket-A SSHIFTEN
N37 AG11 0.01u 1 2
SDATA#19 SDATA18 COREFB+ 60.4RST R24 60.4RST SINTVAL
J33 SDATA19 3 4
SDATA#20 G33 AN17 CPUCLK_R SCANCLK2 5 6
SDATA#21 SDATA20 CLKIN CPUCLK#_R SCANCLK1
G37 SDATA21 CLKIN AL17 7 8
SDATA#22 E37 301ST
SDATA#23 SDATA22 CPUCLK_R 680P C216 270-8p4r
G35 SDATA23 RSTCLK AN19 CPUCLK0 {3}
SDATA#24 Q33 AL19
SDATA#25 SDATA24 RSTCLK
N33 SDATA25
SDATA#26 L33 AL21 CLKOUT CPUCLK#_R 680P C217
SDATA#27 SDATA26 K7CLKOUT CPUCLK-0 {3}
N35 AN21 CLKOUT#
SDATA#28 SDATA27 K7CLKOUT
L37 SDATA28
SDATA#29 J37 VCORE
SDATA#30 SDATA29 VCC2_5 0.5 *
A37 SDATA30 ANALOG AJ13
SDATA#31 E35 VCORE
SDATA#32 SDATA31 VREFMODE VCORE RN5 R27
E31 SDATA32 SYSVREFMODE AA5
SDATA#33 E29 W5 VREF_SYS FID3 1 2 100ST
SDATA#34 SDATA33 VREF_SYS FID2 VREF_SYS
A27 SDATA34 3 4
C SDATA#35 A25 AC5 ZN 100ST 100ST FID1 5 6 C
SDATA#36 SDATA35 ZN ZP FID0 CB2 CB1 R30
E21 SDATA36 ZP AE5 7 8
SDATA#37 C23 100ST
SDATA#38 SDATA37 PLLBP# R25 R26 330-8p4r 39p 0.1u
C27 SDATA38 PLLBYPASS AJ25
SDATA#39 A23 AN15
SDATA#40 SDATA39 PLLBYPASSCLK
A35 SDATA40 PLLBYPASSCLK AL15
SDATA#41 C35 VCORE
SDATA#42 SDATA41 PLLMON1 100ST 100ST RN6 680-8p4r
C33 SDATA42 PLLMON1 AN13
SDATA#43 C31 AL13 PLLMON2 CPUINIT# 1 2
SDATA#44 SDATA43 PLLMON2 PLLTEST# IGNNE# VCORE
A29 SDATA44 PLLTEST AC3 3 4
SDATA#45 C29 R28 R29 CPURST# 5 6
SDATA#46 SDATA45 C218 39P A20M#
E23 SDATA46 7 8
SDATA#47 C25 S1 SCANCLK1 R31 for internal
SDATA#48 SDATA47 SCANCLK1 SCANCLK2 X_1K VREFSYS
E17 SDATA48 SCANCLK2 S5
SDATA#49 E13 S3 SINTVAL RN7 680-8p4r VREFMODE
SDATA#50 SDATA49 SCANINTEVAL SSHIFTEN SMI#
E11 SDATA50 SCANSHIFTEN Q5 1 2
SDATA#51 C15 NMI 3 4 R32
SDATA#52 SDATA51 INTR
E9 SDATA52 DBRDY AA1 5 6
SDATA#53 A13 AA3 DBREQ# STPCLK# 7 8 270
SDATA#54 SDATA53 DBREQ FLUSH#
C9 SDATA54 FLUSH AL3
SDATA#55 A9
SDATA#56 SDATA55 TCK FLUSH# R34 680
SDATA#57
C21 SDATA56 TCK Q1
TDI PLLMON1 R37 56
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