Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6507
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8 7 6 5 4 3 2 1
Version 5.0
Cover Sheet
Block Diagram
1
2
MS-6507 11/20/2001 Update
INTEL (R) Brookdale Chipset
Power Delivery Map 3
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
GPIO Spec. 4
Clock ICS950213AF & ATA100 IDE CONNECTORS 5
mPGA478-B INTEL CPU Sockets 6-7
INTEL Brookdale-E MCH -- North Bridge 8-9
DDR DIMMM1,2 10 CPU:
Willamette/Northwood mPGA-478B Processor
DDR Damping & DDR Termination 11
INTEL ICH4 -- South Bridge 12-13
C
System Brookdale Chipset: C
Ac'97 Codec and Audio Connector & Game Port 14
INTEL MCH (North Bridge) +
AGP 4X SLOT (1.5V) 15 INTEL ICH2 (South Bridge)
PCI SLOT 1 & 2 & 3 16 On Board Chipset:
Realtek RTL8100(L) LAN 17 BIOS -- FWH
LPC I/O W83627HF 18 LPC Super I/O -- W83627HF
FWH & CNR Connector 19 Clock Generation -- ICS950213AF
USB & FAN Connectors 20 AC'97 Codec -- AvanceLogic
B AC201A/AC202A B
Front Panel & Connectors 21
ACPI Controller 22 Expansion Slots:
AGP2.0 SLOT * 1
L6719B CPU Power ( PWM )-VRM9.0 23
PCI2.2 SLOT * 3
IO Connectors 24 CNR 2.2 SLOT * 1
JUMPER SETTING 25
LAYOUT GUIDE 26-30
A A
Title Rev
Micro-Star MS-6507 5.0
Document Number
Cover Sheet
Last Revision Date:
Friday, December 21, 2001 Sheet 1 of 30
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
(478PINS)
(100/133MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
9.0 Socket (mPGA478-B) (100/133MHz)
CONN
(400/533MHz) Scalable Bus Scalable Bus/2
AGP 4X (66MHz) AGP
4X(1.5V) AGP 4X
(1.5V) MCH: Memory
AGP CONN
Controller HUB
(593PINS/FCBGA) (200/266MHz)
DDR DIMM 1:2
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C Heceta Hardware SM Bus C
Monitor PCI (33MHz)
ICH4: I/O
PCI Slots 1:3
(360PINS/EBGA)
Controller HUB
IDE CONN 1&2
PCI Lan /
(48MHz) RJ-45
RealTek
8100BL Connector
(33MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3
AC '97 Audio
FWH: Firmware HUB
Codec Line Out
SIO
Telephone In
MIC In
B Audio In B
Line In
PS2 Mouse & Parallel (1) Floppy Disk
Keyboard Serial (2) Drive CONN CD-ROM
A A
Title Rev
Micro-Star MS-6507 5.0
Document Number
Block Diagram
Last Revision Date:
Friday, December 21, 2001 Sheet 2 of 30
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Delivery Map
D D
ATX 12V POWER Supply
3.3V 5V 5VSB 12V
1A
VRM9.2 Processor Core
Processor Vtt
Power
Translator
1.5V VREG MCH Core 1.5V
ACPI IC
MCH Vtt
MCH AGP
C OP 1.8V VREG MCH HUB Interface 1.8V C
MCH Memory DDR 2.5V
POWER CONSUMPTION
3.3V
DUAL VCCP VCC_AGP VCC1_8 VCC3_DIMM VCC3 VCC5 VCC5_SB +12V -12V
FET DDR System Memory 2.5V CPU 69.0A 0 0 0 0 0 0 NOTE4 0
3.3V VREG PMCH 2.4A NOTE1 0.2A 2.0A 0 0 0 0 0
ICH2 0 0 NOTE3 0 NOTE3 0 NOTE3 0 0
CY28324 0 0 0 0 0 0 0 0 0
AD1885 0 0 0 0 0 0 0 0
ICH2 Core 1.8V FWH -SST 0 0 0 0 0
W83627HF 0 0 0 0 0 0 0 0
ICH2 I/O 3.3V HIP6301 0 0 0 0 0 0 0
HIP6602A 0 0 0 0 0 0
ICH2 Resume 3.3V HIP6601A 0 0 0 0 0 0 0 0 0
SC1547 0 0 0 0 0 0 0
1.8V VREG ICH2 Resume I/O 1.8V DIMM 0 0 0 NOTE2 0 NOTE2 0 0
AGP 0 8.0A 0 0 6.0A 2.0A ? 1.0A 0
5V TO 3.3V ICH2 RTC 3.3V PCI 0 0 0 0 0 0 0 0
USB 0 0 0 0 0
RESISTOR USB HUB 0 0 0 0 0 0 0 0 0
ICH2 5V
FAN 0 0 0 0 0 0 0 0 0
TTL 0 0 0 0 0 0 0 0 0
AMPLIFIER 0 0 0 0 0 0 0
OTHER 0 0 0 0 0 0
B B
FWH 3.3V
NOTE1 --- MCH
VCC_AGP = VCC1_5 (1.5A) + VCC_AGP (0.37A)
LPC Super I/O 3.3V
NOTE2 --- DIMM
S0 STATE --- 2.0A * 3 = 6.0A ---> VCC3
S1/S3 STATE --- 200mA * 3 = 600mA ---> VCC3_SB
CLOCK GEN 3.3V VCC3_SB --> 600mA*3.3V/5V=396mA --> VCC5_SB
NOTE3 --- ICH2
Power S0 S1 S3/S4/S5
HARDWARE AUDIO 3.3V 1.8V 300mA 100mA N/A
1.8V_LAN 36mA 28mA N/A
VCC1_8SB 45mA 30mA 7mA
VCC3 410mA 5mA N/A
PCI LAN 3.3V/2.5V VCC3+562ET 230mA 210mA N/A
VCC3_SB 25mA 0.6mA N/A
VCC3_SB =
5VDual For USB and K/B VCC1_8SB =
VCC5_SB = VCC3_SB + VCC1_8SB
A A
Title Rev
Micro-Star MS-6507
Document Number
Power Delivery Map
Last Revision Date:
Friday, December 21, 2001 Sheet 3 of 30
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
D D
ICH4
GPIO Pin Type Function
GPIO 0 I Non Connect
GPIO 1 I Non Connect
GPIO 2~4 I Not Implemented
DEVICE ICH INT Pin IDSEL
GPIO 5 I Non Connect
GPIO 6 I AC97 Enabled/Disabled
FWH PCI Slot 1 INTA# AD16
GPIO Pin Type Function INTB#
GPIO 7 I None
INTC#
C
GPI 0 I ATA IDE 1 Detect C
GPIO 8 I LAN Wake Up INTD#
GPI 1 I ATA IDE 2 Detect
GPIO 9 I AC'97 Serial Data In
PCI Slot 2 INTB# AD17
GPI 2 I Reserved
GPIO 10 I Non Connect INTC#
GPI 3 I Reserved INTD#
GPIO 11 I Non Connect
INTA#
GPIO 12 I External SMI
PCI Slot 3 INTC# AD18
GPIO 13 I LPC PME
INTD#
GPIO 14~15 I Not Implemented INTA#
INTB#
GPIO 16 O Non Connect
GPIO 17 O Non Connect PCI Lan INTC#/INTF# AD29
B GPIO 18 O Not Implemented B
GPIO 19 O Not Implemented
GPIO 20 O Non
GPIO 21 O Not Implemented
GPIO 22 O Non
GPIO 23 OD BIOS Locked/Unlocked
GPIO 24 O Non
GPIO 25 O Non
GPIO 26 O Non
GPIO 27 I/O Non
A A
GPIO 28 I/O Non
GPIO 29~31 I/O Not Implemented
Title Rev
Micro-Star MS-6507 5.0
Document Number
GPIO Spec.
Last Revision Date:
Friday, December 21, 2001 Sheet 4 of 30
5 4 3 2 1
8 7 6 5 4 3 2 1
for good filtering from 10K~1M
*Trace less 0.5"
CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
CP1 X_COPPER
CPUCLK R1 49.9RST
U1 CPUCLK# R2 49.9RST
FB1 VCC3_C 39 41 R3 33 CPUCLK MCHCLK R4 49.9RST
VCC3 CPU_VDD CPU0 CPUCLK {6}
X_0/0805 R5 33 CPUCLK# MCHCLK# R6 49.9RST
+
CPU0# 40 CPUCLK# {6}
CB1 Rubycon CT1 CB2 CB3
104P 105P 104P 36 38 R7 47 MCHCLK
CPU_GND CPU1 MCHCLK {8}
37 R8 47 MCHCLK# CN1
CPU1# MCHCLK# {8}
D X_ELS10U/16V-B D
46 X_8P4C-10P
MREF_VDD C_STP MCH_66
CB4 3VMREF/CPU_STP# 45
P_STP
Trace less 0.2" ICH_66
1 2
3VMREF#/PCI_STP# 44 3 4
104P 43 49.9ohm for 50ohm M/B impedance AGPCLK 5 6
MREF_GND
7 8
for good filtering from 10K~1M 32 31 1 2 MCH_66
3V66_VDD 3V66_0 MCH_66 {8}
30 RN1 3 4 ICH_66 CN2
3V66_1 ICH_66 {13}
CP2 X_COPPER CB5 8P4R-33 AGPCLK X_8P4C-10P
R9 104P 29
3V66_2 28
27
5
7
6
8
AGPCLK {15} CLOCK STRAPPING RESISTORS SIO_PCLK 8 7
X_0 3V66_GND 3V66_3 FWH_PCLK 6 5
6 FS2 7 8 ICH_PCLK 4 3
FB2 X_0/0805 VCC3V FS2/PCI_F0 FS3
VCC3 9 PCI_VDD FS3/PCI_F1 7 5 6 ICH_PCLK ICH_PCLK {12}
FS4 R10 10K VCC3V 2 1
MODE 4 FWH_PCLK FS3 R11 10K VCC3V
+
MODE/PCI_F2 8 3 FWH_PCLK {19}
CB6 Rubycon CT2 CB7 CB8 RN2 1 2 SIO_PCLK CN3
SIO_PCLK {18}
104P 105P 104P 5 10 FS4 8P4R-33 FS1 R12 10K VCC3V X_8P4C-10P
PCI_GND FS4/PCI0 FS1
11 R13 X_10K PCICLK0 7 8
X_ELS10U/16V-B PCI1 R14 33 PCICLK5 PCICLK1
18 PCI_VDD PCI2 12 PCICLK5 {16} 5 6
14 7 8 PCICLK0 PCICLK2 3 4
PCI3 PCICLK0 {16}
CB9 15 RN3 5 6 PCICLK1 FS0 R15 10K VCC3V PCICLK3 1 2
PCI4 PCICLK1 {16}
104P 13 16 8P4R-33 3 4 PCICLK2 R16 X_10K
PCI_GND PCI5 PCICLK2 {16}
*Put GND copper under Clock Gen. 17 1 2 PCICLK3 PCICLK4
PCI6 PCICLK3 {17}
FS2 R17 10K C1 X_10P
connect to every GND pin 24 R18 X_10K VCC3V
48_VDD FS0 R19 33 ICH_48 PCICLK5 C2 10P
* 40 mils Trace on Layer 4 CB10 FS0/48MHz 22
FS1 R20 33 SIO_48
ICH_48 {13}
MODE R21 X_10K
FS1/24_48MHz 23 SIO_48 {18}
with GND copper around it 104P 21 AUDIO_14 C3 10P
48_GND
* put close to every power pin
C 2 REF_VDD C
* Trace Width 7mils. 48 MUL0 R22 33 ICH_14 MUL0=0 MUL0=1 MUL0 R23 X_10K VCC3V ICH_48 C4 X_10P
MUL0/REF0 ICH_14 {13}
CB11 1 MUL1 R24 33 AUDIO_14 R25 10K SIO_48 C5 10P
MUL1/REF1 AUDIO_14 {14}
* Same Group spacing 15mils 104P 47 Ioh=6*Iref
REF_GND MUL1 R26 10K VCC3V
VCC3_C C6 18P
Voh=0.71V R27 X_10K
* Different Group spacing 30mils 34 CORE_VDD X1 3
* Different mode spacing 7mils on itself CB12 X1 14.318MHZ/32PF
104P 33 4 C7 18P CRST# R28 10K VCC3V ICH_14 C8 10P
CORE_GND X2
SMBCLK 26 35 R29 475RST
{10,18,19,22} SMBCLK SCLK IREF
R30 VTT_GD# SMBDATA 25 SMBCLK R31 1K used only for EMI issue
VCC3 {10,18,19,22} SMBDATA SDATA VCC3
10K 20 CRST# R32 X_0 FP_RST# SMBDATA R33 1K
RST# FP_RST# {13,21,22}
R34 X_1KVTT_GD# 19 42 R35 4.7K VCC3V Trace less 0.2"
VTT_GD# PWR_DN# VCC3V
Q1
VCCP
2N3904S ICS950213AF C_STP R37 X_1K VCC3V
R36 220 P_STP R38 X_1K
R39
VCC3
X
Q2
{6} SKTOCC#
X_2N3904S
SECONDARY IDE BLOCK
PRIMARY IDE BLOCK
R41 4.7K IDE2
ATA100 IDE CONNECTORS R40 4.7K IDE1
YJ220-CW-1
YJ220-CB-1 HD_RST# R42 33 1 2
B B
HD_RST# R43 33 1 2 SDD7 3 4 SDD8
{22} HD_RST# {13} SDD[0..7] SDD[8..15] {13}
PDD7 3 4 PDD8 SDD6 5 6 SDD9
{13} PDD[0..7] PDD[8..15] {13}
PDD6 5 6 PDD9 SDD5 7 8 SDD10
PDD5 7 8 PDD10 SDD4 9 10 SDD11
PDD4 9 10 PDD11 SDD3 11 12 SDD12
PDD3 11 12 PDD12 SDD2 13 14 SDD13
PDD2 13 14 PDD13 SDD1 15 16 SDD14
PDD1 15 16 PDD14 SDD0 17 18 SDD15
PDD0 17 18 PDD15 19
19 {13} SDDREQ 21 22
VCC_AGP 21 22 23 24
{13} PDDREQ {13} SDIOW#
{13} PDIOW# 23 24 {13} SDIOR# 25 26
25 26 27 28 R44 470
{13} PDIOR# {13} SDIORDY
27 28 R45 470 29 30
BSEL0 {6} {13} PDIORDY {13} SDDACK#
R46 29 30 31 32
{13} PDDACK# {12} IRQ15
1K {12} IRQ14 31 32 {13} SDA1 33 34 SD_DET {19}
{13} PDA1 33 34 PD_DET {19} {13} SDA0 35 36 SDA2 {13}
R47 35 36 37 38
FS1 {13} PDA0 PDA2 {13} {13} SDCS#1 SDCS#3 {13}
8.2K 37 38 R48 33 39 40
{13} PDCS#1 PDCS#3 {13} {21} SD_LED
A C R49 33 39 40
{21} PD_LED
R51
6.8K D1 C9 R50 C10
1N4148S R52 C11 R53 C12 R54 8.2K 47P 10K X_473P
{9,15} ST1 VCC5
R/0603 R55 8.2K 47P 10K X_473P
C
VCC5 VCC3
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