Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6566
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8 7 6 5 4 3 2 1
MS-6566 INTEL (R)
Brookdale/ICH2 BRIIKDALE PLATFORM POWER DELIVERYT MAP
3.3V 5V 5VSB1A 12V
CHIPSET
Pentium 4 in 478 pinPackage/Northwood
D
Processor SCHEMATICS PROCESSOR CORE
D
VRM PROCESSOR VTT
Title Page
Cover Sheet 1 MCH CORE 1.5V
Block Diagram 2
1.5V VREG MCH VTT
Processor Sockets 3,4
Clock Synthesizer CK408 5 MCH AGP
MCH BROOKDALE 6,7,8
MCH HUB INTERFACE 1.8V
DIMM 1 & 2 & 3 9,10
ICH2 CPU/AC97/SYS 11 1.8V VREG MCH SYSTEM MEMORY SDRAM 3.3V
ICH2 LPC/USB/PWR 12
IDE1 & IDE2 13
FWHUB 14
PCI Connectors 15,16,17 3.3V VREG
C
USB 18 C
AGP 19 ICH2 CORE 1.8V
CNR RISER 20
ICH2 I/O 3.3V
S/W AUDIO 21
AUDIO GAME PORT 22 1.8V VREG ICH2 RESUME 1.8V
LPC/Flopy Connector 23
ICH2 RESUME I/O 3.3V
Hardware Monitor 24
Parallel Port TERMINATION 25 ICH2 RTC 3.3V
Parallel Port/Serial Port 26
ICH2 5V
KB / MOUSE CONNECTOR 27
PULL UP RESISTOR 28
Front Pannel 29
VRM 9.1 30 3.3 VREG
ACPI POWER 31
B D_LED & OVER VOLTAGE 32 B
DDR DAMPING 33
DDR TERMINATION 34
MANUAL PART 35
FWH 3.3V
VERSION HISTORY 36
GPIO SPEC 37
LPC SUPER I/O 3.3V
CK-408 3.3V
A A
MICRO-STAR
Title
COVER
Size Document Number Rev
Custom MS-6566 0A
Date: Monday, November 26, 2001 Sheet 1 of 37
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power
Supply VRM9.1 Pentium4 Socket478 CK_408 Clock
CONN
Scalable Bus
AGP 4X 4X (266MHz) AGP DIMM 1:3
AGP MCH: Memory
CONN DOUBLE DATA
Controller HUB RATE SDRAM
D D
VRM
AGP
CONN
HUB Interface
Heceta Hardware SM Bus
Monitor ICH2: I/O PCI (33MHz)
Controller HUB
IDE CONN 1&2
LPC Bus AC Link
USB Port 1:3 CNR Riser
Brookdale (Shared slot)
C Chipset C
S/W AUDIO
USB Port 4 FWH: Firmware HUB
FRNL Panel AMP
Winbond I/O
Line Out
Telephone In
MIC In
Audio In
Line In POWER CONSUMPTION
PS2 Mouse & Parallel (1) Floppy Disk
Keyboard Serial (2) Drive CONN CD-ROM
VCCP VCC_AGP VCC1_8 VCC3_DIMM VCC3 VCC5 VCC5_SB +12V -12V
CPU 69.0A 0 0 0 0 0 0 NOTE4 0
PMCH 2.4A NOTE1 0.2A 2.0A 0 0 0 0 0
ICH2 0 0 NOTE3 0 NOTE3 0 NOTE3 0 0
CLOCK 0 0 0 0 0 0 0 0 0
CODEC 0 0 0 0 0 0 0 0
FWH 0 0 0 0 0 0 0 0
LAN 0 0 0 0 0 0 0 0
SIO 0 0 0 0
782D 0 0 0 0
SC2433 0 0 0 0 0 0 0 0 0
SC1205 0 0 0 0 0 0 0 0 0
SC1547 0 0 0 0 0 0
B DIMM 0 0 0 NOTE2 0 0 NOTE2 0 0 B
CNR 0 0 0 0 0 0
AGP 0 8.0A 0 0 6.0A 2.0A ? 1.0A 0
PCI 0 0 0 0 0 0 0
USB 0 0 0 0 0 0 0 0 0
FAN 0 0 0 0 0 0 0 0 0
TTL 0 0 0 0 0 0 0
OTHER 0
NOTE1 --- MCH
VCC_AGP = VCC1_5 (1.5A) + VCC_AGP (0.37A)
NOTE2 --- DIMM
S0 STATE --- 2.0A * 3 = 6.0A ---> VCC3
S1/S3 STATE --- 200mA * 3 = 600mA ---> VCC3_SB
VCC3_SB --> 600mA*3.3V/5V=396mA --> VCC5_SB
NOTE3 --- ICH2
Power S0 S1 S3/S4/S5
1.8V 300mA 100mA N/A H/W Project Leader : Andy Chen
1.8V_LAN 36mA 28mA N/A H/W Project Engineer : Prudence Wang
VCC1_8SB 45mA 30mA 7mA
VCC3 410mA 5mA N/A
VCC3+562ET 230mA 210mA N/A
VCC3_SB 25mA 0.6mA N/A
VCC3_SB =
VCC1_8SB =
A A
VCC5_SB = VCC3_SB + VCC1_8SB
MICRO-STAR
Title
Block Diagram
Size Document Number Rev
Custom MS-6566 0A
Date: Monday, November 26, 2001 Sheet 2 of 37
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCCP
R67
HA#[3..31]
6 HA#[3..31]
49.9
VID[0..4] 32
VCCP
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
VID3
VID4
VID2
VID1
VID0
R68 C90 C73 C71
R26
D D
AD26
AC26
AE25
100 1u 220p 1u
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
49.9
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
Y1
T5
T4
T2
T1
L2
L3
L6
HDBI#[0..3] U2A
6 HDBI#[0..3]
DBR
VCC_SENSE
VSS_SENSE
ITP_CLK1
ITP_CLK0
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
VID4#
VID3#
VID2#
VID1#
VID0#
HDBI#0 E21 C6 C44 C46
HDBI#1 DBI0# R6
G25 DBI1# GTLREF3 AA21
HDBI#2 P26 AA6 220p 220p 1u
HDBI#3 DBI2# GTLREF2 100
V21 DBI3# GTLREF1 F20
GTLREF0 F6
AC3 IERR#
V6 AB4 BPM#5 RN2
FERR# MCERR# BPM5# BPM#4 BPM#0
11,28 FERR# B6 FERR# BPM4# AA5 1 2
STPCLK# Y4 Y6 BPM#5 3 4
11 STPCLK# STPCLK# BPM3#
AA3 AC4 BPM#1 5 6
HINIT# BINIT# BPM2# BPM#1 BPM#4
11,14,28 HINIT# W5 INIT# BPM1# AB5 7 8 VCCP
AB2 AC6 BPM#0
C351 RSP# BPM0#
56
HDBSY# H5 H3 HREQ#4 HREQ#[0..4]
10000p 6 HDBSY# DBSY# REQ4# HREQ#[0..4] 6
HDRDY# H2 J3 HREQ#3
6 HDRDY# DRDY# REQ3#
HTRDY# J6 J4 HREQ#2
6 HTRDY# TRDY# REQ2#
K5 HREQ#1
HADS# REQ1# HREQ#0
6 HADS# G1 ADS# REQ0# J1
HLOCK# G4 AD25
C 6 HLOCK# LOCK# TESTHI12 C
HBNR# G2 A6
6 HBNR# BNR# TESTHI11
HIT# F3 Y3 R515 4.7K
6 HIT# HIT# TESTHI10
HITM# E3 W4 R25 4.7K
6 HITM# HITM# TESTHI9
HBPRI# D2 U6 R30 4.7K
6 HBPRI# BPRI# TESTHI8
HDEFER# E2 AB22
6 HDEFER# DEFER# TESTHI7
TESTHI6 AA20
TDI_CPU C1 AC23 R62 4.7K
28 TDI_CPU TDI TESTHI5
TESTHI4 AC24
TESTHI3 AC20
TDO_CPU D5 AC21
28 TDO_CPU TDO TESTHI2
AA2 R29 4.7K
TESTHI1 VCCP
TESTHI0 AD24
TMS_CPU F7
28 TMS_CPU TMS
AF23 CPUCLK#
BCLK1# CPUCLK# 5
TRST#_CPU E6 AF22 CPUCLK
28 TRST#_CPU TRST# BCLK0# CPUCLK 5
TCK_CPU D4 F4 HRS#2 HRS#[0..2]
28 TCK_CPU TCK RS2# HRS#[0..2] 6
G5 HRS#1
VTIN2 RS1# HRS#0
23,24 VTIN2 B3 THERMDA RS0# F1
VAGND C4
23,24 VAGND THERMDC
THERMTRIP# A2 V5
28 THERMTRIP# THERMTRIP# AP1#
AP0# AC1
R13 HBR#0
BR0# H6 HBR#0 6,28
B
VCCP C3 PROCHOT# B
IGNNE# B2 P1 R33
11 IGNNE# IGNNE# COMP1
SMI# B5 L24 SHORT TRACE
11 SMI# SMI# COMP0
62 A20M# C6 49.9
11 A20M# A20M
SLP# AB26 L25 R64
11 SLP# SLP# DP3#
A22 RESERVED DP2# K26
A7 RESERVED DP1# K25
AD2 J26 49.9
RESERVED DP0#
AD3 RESERVED
PROCHOT# AE21 R5 HADSTB#1
12,23 PROCHOT# RESERVED ADSTB1# HADSTB#1 6
AF24 L5 HADSTB#0
RESERVED ADSTB0# HADSTB#0 6
AF25 W23 HDSTBP#3
RESERVED DSTBP3# HDSTBP#3 6
VCCP CPU_PWRGD AB23 P23 HDSTBP#2
12,28 CPU_PWRGD PWRGOOD DSTBP2# HDSTBP#2 6
HCPURST# AB25 J23 HDSTBP#1
6,28 HCPURST# RESET# DSTBP1# HDSTBP#1 6
HD#63 AA24 F21 HDSTBP#0
D63# DSTBP0# HDSTBP#0 6
HD#62 AA22 W22 HDSTBN#3
D62# DSTBN3# HDSTBN#3 6
R14 HD#61 AA25 R22 HDSTBN#2
D61# DSTBN2# HDSTBN#2 6
Q3 HD#60 Y21 K22 HDSTBN#1
4.7K D60# DSTBN1# HDSTBN#1 6
3 HD#59 Y24 E22 HDSTBN#0
D59# DSTBN0# HDSTBN#0 6
2 HD#58 Y23 E5 LINT1
D58# LINT1 LINT1 11
1 HD#57 W25 D1 LINT0
D57# LINT0 LINT0 11
HD#56 Y26
BSEL0
BSEL1
HD#55 D56# PGA-S478-F02
W26
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
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