Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6596
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8 7 6 5 4 3 2 1
Cover Sheet 1
Block Diagram 2
D
CLOCK GEN
AMD CPU Sockets 462
3
4-5
MS-6596 Ver : 4.00 D
Via VT8375 KM266 North Bridge 6-8 VIA KT400 + VT8235 Chipset
DDR SLOT 9
DDR TERMINATOR 10
CPU:
AGP SLOT 11 AMD Athlon XP / Athlon / Duron Socket 462
Via VT8235 South Bridge 12 - 14
PCI SLOTS 1,2&3 15 System Chipset:
C C
LAN 16 VIA VT8377 (KT400 ) + VT8235
IDE CONNECTOR 17
On Board Chipset:
USB & KB/MS CONNECTOR 18
LPC Super I/O -- W83697HF
AC'97 CODEC 19 Lan : Via PHY VT6103
AUDIO CONNECTOR 20
FLASH ROM & FAN CONNECTOR 21 Expansion Slots:
B
LPC I/O(W83697HF) 22 AGP 3.0 Slot * 1 B
PARALLEL & SERIAL CONN. 23 DDR Slot * 2
PCI 2.2 Slot * 3
MS-5 ACPI CONTROLLER, REGULATORS 24
ATX POWER CON, FRONT PANEL & Thermal Trip 25
VRM 9.0 26
I1394A (VT6307) CONTROLLER / CONNECTOR 27
DECOUPLING CAPACITORS 28
HISTORY 29
A A
30
MICRO-STAR INT'L CO.,LTD.
31 Title
COVER PAGE
32 Size
Custom
Document Number Rev
4.00
MS-6596
Date: Monday, February 24, 2003 Sheet 1 of 29
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
System Block Diagram
+ 12V
- 12V
+ 5V
D ATX CONN D
SOCKET-462 - 5V
3.3V
VCC5SBY
Host Bus
(100/133MHz)
( 100/133MHz) VCC5SBY
VCC3SBY VCCM
8 X / 4X/2X (66MHz) VCC3
AGP Connector Via VT8377
2 DDR DIMM MODUAL
VCC25SBY
V-Link
C 8x/4x/2x C
DDR_VTT
PCI (33MHz) (66MHz)
PCI SLOT 3 P CI SLOT 2 P CI SLOT 1 I1394A AC'97 Link (14.318MHz) AC'97 VCC2_5
AUDIO CODEC
ALC650
U L T R A DMA 33/66/100/133
Via VT8235 VDDQ
IDE 1 IDE 2 PS/2 USB2.0
KEYBOARD
/MOUSE
VCCA_PLL
MII USB 0 USB 2 USB 4
LPC
LAN PHY Bus
USB 1 USB 3 USB 5
FAN CONTROL V O LTAGE MONITOR VCC5SBY
CPU SYS 5VDUAL KBUVCC
B B
VCC5
FAN FAN
T E M P ERATURE MONITOR
LPC Super I/O
FLASH VCORE
ROM
GPIO SERIAL PARALLEL FLOPPY
A A
MICRO-STAR INT'L CO.,LTD.
Title
System Block Diagram
Size Document Number Rev
Custom 4.00
MS-6596
Date: Monday, February 24, 2003 Sheet 2 of 29
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Main Clock Generator
D D
VCC3 U13
CP12 B y - P a s s Capacitors Place
5 48 7 8 CPUCLK1
VDDAGP CPUCLK_PPT 49 CPUCLK1 6 n e a r t o the Clock Outputs
16 RN72 5 6 CPUCLK-1
VDDPCI CPUCLK_PPC CPUCLK-1 6
X_COPPER 22 10-8P4R 3 4 CPUCLK-0
VDD48M CPUCLK-0 4
51 53 1 2 CPUCLK0 AGPCLK0 C217 10p
VDDCPU CPUCLKST 52 CPUCLK0 4
L36 CB89 CB104 CB103 CB102 CB91 55 VLCLK C229 10p
X_80-0805 1u 1u 1u 1u 0.1u VDDREF CPUCLKSC AGPCLK1 C218 10p
RN69 1 2 DDRCLK0 DDRCLK0 9
2 44 10-8P4R 3 4 DDRCLK-0 CN14 X_10p-8P4C
GND2 DDRT0 DDRCLK-0 9
EC53 9 43 5 6 DDRCLK1 PCICLK3 1 2
GND9 DDRC0 DDRCLK1 9
X_10u/16V ECSMD 13 42 7 8 DDRCLK-1 SIOPCLK 3 4
GND13 DDRT1 DDRCLK-1 9
19 41 PCICLK2 5 6
33 GND48M DDRC1 38 RN70 1 2 DDRCLK2 PCICLK1 7 8
GND33 DDRT2 DDRCLK2 9
39 37 10-8P4R 3 4 DDRCLK-2
GND39 DDRC2 DDRCLK-2 9
47 36 5 6 DDRCLK3 1394_PCLK C348 X_10p
GNDI DDRT3 DDRCLK3 9
54 35 7 8 DDRCLK-3
GND54 DDRC3 DDRCLK-3 9
32 PCLKSB C215 X_10p
DDRT4 31 1 2 DDRCLK4 APICCPU C185 X_10p
DDRC4 DDRCLK4 9
L38 X_80-0805 23 30 RN71 3 4 DDRCLK-4 APICSB C216 X_10p
VCC3 AVDD DDRT5 DDRCLK-4 9
CB96 CB95 29 10-8P4R 5 6 DDRCLK5 SBCLK14 C214 X_10p
DDRC5 DDRCLK5 9
CB94 CP13 0.1u 1u 24 7 8 DDRCLK-5 USBCLK C220 X_10p
AGND DDRCLK-5 9
X_0.1u 45 SIO48M C219 X_10p
BUFFER_IN DCLKO
C DCLKO 7 C
X_COPPER VCC2_5 50 46 R187 22
VDDI FBOUT DCLKI 7
VCC2_5 R157 X_4.7K VCC2_5
L35 6 MODE R246 22 AGPCLK0 DCLKO R173 X_4.7K
AGP0/MODE 7 AGPCLK0 8
VADDR25 34 SELCPU R270 22 VLCLK
VDD3.3/2.5-34 AGP1/SEL_CPU 8 VLCLK 12
X_80-0805 R248 22 AGPCLK1
AGP2/PCI_STOP# AGPCLK1 11
CB90 CB92 40
VDD3.3/2.5-40 RN78 22-8P4R
CP11
CB93 1u 1u 10 FS1 1 2 PCICLK3 B y - P a s s Capacitors Place
PCICLK_F/FS1 PCICLK3 15
0.1u 11 SELDDR# 3 4 SIOPCLK
X_COPPER PCICLK0/SEL_SD_DDR# 12 MULTSEL0 5 6 PCICLK2 SIOPCLK 22 n e a r t o the Clock Outputs
PCICLK1/MULTSEL0 PCICLK2 15
14 7 8 PCICLK1 CN11 10p-8P4C
PCICLK2 PCICLK1 15
15 DDRCLK0 1 2
27 PCICLK3 17 R396 22 1394_PCLK DDRCLK-0 3 4
9,13,24,25 SMBCLK SCLK PCICLK4 1394_PCLK 27
28 18 R241 22 PCLKSB DDRCLK1 5 6
9,13,24,25 SMBDAT SDATA PCICLK5/CPU_STP# PCLKSB 12 DDRCLK-1 7 8
R223 X_0 26 20 FS3 R252 22 USBCLK
24,25,26 FP_RST# RESET/PD# 48M/FS3 21 USBCLK 14
FS2 R271 22 SIO48M CN12 10p-8P4C
24_48M/FS2 SIO48M 22
DDRCLK2 1 2
R243 22 APICSB DDRCLK-2 3 4
APICSB 12
R216 475RST 25 1 FS0 R254 33 SBCLK14 DDRCLK3 5 6
IREF REF0/FS0 SBCLK14 13
R266 33 DDRCLK-3 7 8
AC97CLK 19
56 REF1
VTT_PWRGD#/REF1
XOUT
R196 62 APICCPU CN10 10p-8P4C
XIN
APICCPU 4
R197 261RST DDRCLK4 1 2
DDRCLK-4 3 4
B B
CY28341-2 A DDRCLK5 5 6
DDRCLK-5 7 8
3
4
Y1
MULTSEL0 R231 X_4.7K
SELCPU R247 4.7K CN13 10p-8P4C
VCC3 14M-32pf-HC49S-D SELDDR# R249 4.7K CPUCLK0 1 2
CPUCLK-0 3 4
C209 C193 CPUCLK-1 5 6
22p 22p
5
CPUCLK1 7 8
REF1 1 R244 4.7K FS0
VCC3
4 APICSB
2 R272 10K FS1 R250 X_2.7K
13 FS1_S
U11
5
X_NC7SZ08P5X-SOT23_ R283 10K FS3 R251 X_4.7K
13 FS3_S
3
FS2 R253 4.7K
R207 X_22
VCC2_5
5
REF1 1
4 R198 X_22 APICCPU
2
U10
A X_NC7SZ08P5X-SOT23_
5 A
3
MICRO-STAR INT'L CO.,LTD.
Title
CLOCK GEN
Size Document Number Rev
Custom 4.00
MS-6596
Date: Monday, February 24, 2003 Sheet 3 of 29
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCC3
CPU1A
SDATA#0 AA35 AE1 VCORE
6 SDATA#[0:63] SDATA#1 SDATA0 A20M A20M# 12
W37 AG1 FERR R8
SDATA#2 W35 SDATA1 FERR AJ3 510
SDATA#3 Y35 SDATA2 INIT AL1 CPUINIT# 12 R21
SDATA#4 SDATA3 INTR INTR 12 X_680
U35 AJ1
SDATA#5 SDATA4 IGNNE IGNNE# 12 FERR# 12
U33 AN3 VCORE
C
SDATA#6 SDATA5 NMI NMI 8
S37 AG3
SDATA#7 SDATA6 RESET CPURST# 24 FERR R15 1K B
S33 AN5
SDATA#8 SDATA7 SMI SMI# 12
AA33 AC1 STPCLK# Q1 TRST# R22 510
SDATA#9 SDATA8 STPCLK STPCLK# 12
AE37 NPN-3904LT1-SOT23 PLLTEST# R30 510
SDATA#10 SDATA9
E
D AC33 AE3 PWRGD_CPU 24 D
SDATA#11 AC37 SDATA10 PWROK RN14
SDATA#12 Y37 SDATA11 DBREQ# 1 2
SDATA#13 AA37 SDATA12 N1 TCK 3 4
SDATA13 PICCLK N3 APICCPU 3
SDATA#14 AC35 TMS 5 6
SDATA#15 SDATA14 PICD0/BYPASSCLK N5 APICD0 12
S35 VCORE TDI 7 8
SDATA#16 SDATA15 PICD1/BYPASSCLK APICD1 12
Q37
SDATA#17 SDATA16 COREFB- 510-8P4R
Q35 AG13 COREFB- 26
SDATA#18 N37 SDATA17 COREFB- AG11 COREFB+
SDATA#19 SDATA18 COREFB+ COREFB+ 26
J33 RN10
SDATA#20 SDATA19 CPUCLK_R R67 R71 C50 SSHIFTEN
G33 AN17 1 2
SDATA#21 G37 SDATA20 CLKIN AL17 CPUCLK#_R 60.4RST 60.4RST 0.01u SINTVAL 3 4
SDATA#22 E37 SDATA21 CLKIN SCANCLK2 5 6
SDATA#23 SDATA22 Place Near
G35 AN19 R68 SCANCLK1 7 8
SDATA#24 Q33 SDATA23 RSTCLK AL19 socket-A 301RST
SDATA#25 N33 SDATA24 RSTCLK 270-8P4R
SDATA#26 L33 SDATA25 AL21 CLKOUT CPUCLK_R C45 680P
SDATA26 K7CLKOUT AN21 CPUCLK0 3
SDATA#27 N35 CLKOUT#
SDATA#28 L37 SDATA27 K7CLKOUT
SDATA#29 J37 SDATA28 CPUCLK#_R C49 680P
SDATA29 CPUCLK-0 3
SDATA#30 A37 AJ13
SDATA#31 E35 SDATA30 ANALOG
SDATA#32 E31 SDATA31 AA5 VREFMODE VCORE
SDATA#33 E29 SDATA32 SYSVREFMODE W5 VREF_SYS VCC2_5
SDATA#34 SDATA33 VREF_SYS VCORE
A27
SDATA#35 A25 SDATA34 AC5 ZN RN6 R18
SDATA35 ZN AE5 0 .5 * VCORE
SDATA#36 E21 ZP FID3 1 2 100RST
SDATA#37 SDATA36 ZP FID2 VREF_SYS
C23 3 4
SDATA#38 C27 SDATA37 AJ25 PLLBP# R63 R57 FID1 5 6
C C
SDATA#39 A23 SDATA38 PLLBYPASS AN15 100RST 100RST FID0 7 8 R13
SDATA#40 SDATA39 PLLBYPASSCLK AL15 CB3 CB4 100RST
A35
SDATA#41 C35 SDATA40 PLLBYPASSCLK 330-8P4R 39p 0.1u
SDATA#42 C33 SDATA41 AN13 PLLMON1
SDATA#43 C31 SDATA42 PLLMON1 AL13 PLLMON2 R59 R61
SDATA#44 SDATA43 PLLMON2 AC3 PLLTEST# 100RST 100RST VCORE
A29
SDATA#45 C29 SDATA44 PLLTEST RN8 680-8P4R
SDATA#46 E23 SDATA45 CPUINIT# 1 2
SDATA#47 SDATA46 SCANCLK1 IGNNE# VCORE
C25 S1 3 4
SDATA#48 E17 SDATA47 SCANCLK1 S5 SCANCLK2 CPURST# 5 6
SDATA#49 E13 SDATA48 SCANCLK2 S3 SINTVAL C13 39P A20M# 7 8
SDATA#50 SDATA49 SCANINTEVAL Q5 SSHIFTEN R26
E11
SDATA#51 C15 SDATA50 SCANSHIFTEN X_1K
SDATA#52 E9 SDATA51 AA1 RN7 680-8P4R VREFMODE
SDATA#53 A13 SDATA52 DBRDY AA3 DBREQ# SMI# 1 2
SDATA#54 SDATA53 DBREQ AL3 FLUSH# NMI
C9 3 4
SDATA#55 A9 SDATA54 FLUSH INTR 5 6 R24
SDATA55 for
SDATA#56 C21 Q1 TCK STPCLK# 7 8 270
SDATA#57 SDATA56 TCK U1 TDI internal
A21
SDATA#58 E19 SDATA57 TDI U5 VREFSYS
SDATA#59 C19 SDATA58 TDO Q3 TMS FLUSH# R39 680
SDATA59 TMS U3 VREFMODE=Low=No voltage scaling
SDATA#60 C17 TRST# PLLMON1 R51 56
SDATA#61 A11 SDATA60 TRST PLLMON2 R47 56
SDATA#62 A17 SDATA61
SDATA#63 A15 SDATA62 L1 VID0 RN27 680-8P4R
SDATA63 VID0 VID0 26
L3 VID1 1 2 VCORE
VID1 VID1 26
L5 VID2 AIN#0 3 4 ZN R33 40.2RST
6 DICLK#[0:3] VID2 VID2 26
DICLK#0 W33 L7 VID3 AIN#1 5 6
B SDATAINCLK0 VID3 VID3 26 B
DICLK#1 J35 J7 VID4 PLLBP# 7 8 ZP R37 56.2RST
SDATAINCLK1 VID4 VID4 26
DICLK#2 E27
DICLK#3 E15 SDATAINCLK2 CPURST# R32 X_270
SDATAINCLK3 FID0 m a tch the transmission line
W1 FID0 13 RESERVE
DIVAL# AN33 FID0 W3 FID1
6 DIVAL# SDATAINVAL FID1 FID1 13 Push-pull compensation circuit
Y1 FID2
DOCLK#0 AE35 FID2 Y3 FID3 FID2 13 COREFB+ R48 10K
6 DOCLK#[0:3] C37 SDATAOUTCLK0
DOCLK#1 FID3 FID3 13 VCORE
DOCLK#2 A33 SDATAOUTCLK1 C24
DOCLK#3 C11 SDATAOUTCLK2 U37 4.7u-1206
SDATAOUTCLK3 SCHECK0 Y33
DOVAL# AL31 SCHECK1 L35 COREFB- R54 10K
SDTATOUTVAL SCHECK2 E33 RN21 100-8P4R VCORE
AIN#0 SCHECK3
AJ29 E25 8 7
AIN#1 AL29 SADDIN0 SCHECK4 A31 CLKOUT 6 5
AIN#2 AG33 SADDIN1 SCHECK5 C13 CLKOUT# 4 3
6 AIN#[2:14] AIN#3 AJ37 SADDIN2 SCHECK6 A19 AIN#0 R82 X_680 2 1
AL35 SADDIN3
AIN#4 SCHECK7
AIN#5 AE33 SADDIN4 J1 AIN#1 R81 X_680
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