Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6597
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1
Cover Sheet
Block Diagram
1
2
(MS-6597) Version: 1.0
AMD 462pins SocketA CPU - Signals 3 Nvidia (R) Crush11(nForce IGP 64) + MCP2/2H Chipset
AMD Althon/Duron/Morgan/Palomino Socket 462 Processor
AMD 462pins SocketA CPU - Power 4
CRUSH11 - Host Signals 5 CPU:
CRUSH11 - Memory Signals 6 AMD Duron/Morgan/Athlon & XP Processor
CRUSH11 - AGP , LDT Signals & PLL DELAY 7
System Chipset:
CRUSH11 - Power & CPU VID Select 8
Nvidia nForce IGP 64 (North Bridge)
MCP2 - CPU & PCI & LDT & IDE Signals 9
MCP2/2H Wep (South Bridge)
MCP2 - MAC & USB & LPC & AC'97 Signals 10
On Board Chipset:
LPC I/O - W83627HF 11
BIOS -- LPC EEPROM
AC97 Audio 12 AC'97 Codec -- ALC650E
A
LAN & LPC Flash EEPROM 13 LPC Super I/O -- W83627HF-AW A
LAN -- ICS1893 PHY
DDR System Memory 14
I1394 -- FW803 PHY ( Option )
AGP 1.5V Slot, LDT Regulator 15
Expansion Slots:
PCI Slots 16
AGP2.0 SLOT (1.5V) * 1
ATA33/66/100 IDE & Video Connectors 17 PCI2.2 SLOT * 3
FAN & USB Connectors 18 PWM Controller:
I1394 PHY & Connectors 19 L6911D
ATX & Front Panel 20 ACPI:
ACPI (MS5) Controller 21 MS5
VRM 9.0 - L6911D 22
GPIO 23
Power Delivery Map & MANUAL 24
MICRO-STAR INt'L CO., LTD.
Revision History 1 25 MSI
Title
COVER SHEET
Size Document Number Rev
0B
(MS-6597)
Date: Tuesday, October 22, 2002 Sheet 1 of 25
1
1
VRM 9.0
L6911D
Single Phase
462-Pin Socket Processor Block Diagram
PWM
K7 FSB
( 100/133MHz)
(66MHz)
4X w/Fast Write
AGP 1.5V
Connector 64bit DDR
2 DDR
CRUSH 11 DIMM
( 200/266 MHz)
Analo g Modules
Video
Out
LDT Link
(200 MHz)
IDE Prim ary UltraDMA 33/66/100
PCI CNTRL
PCI Slot 1
PCI Slot 2
PCI Slot 3
IDE Seco ndary
MCP-2 PCI ADDR/DATA
USB Port 0
A A
PCI (33MHz)
USB Port 1
USB Port 2 USB
(24MHz)
LPC Bus
USB Port 3 (48MHz)
USB Port 4
LPC SIO
USB Port 5
W83627HF-AW
AC'97 Link (14.318MHz)
ALC650E
(33MHz)
AC'97 Codec
MII ( 2.5/25 MHz)
10/100BaseT
I C S1893 Flash Keyboard Floopy Parallel Seria l
Mouse
MICRO-STAR INt'L CO., LTD.
MSI
Title
BLOCK DIAGRAM
Size Document Number Rev
0B
(MS-6597)
Date: Tuesday, October 22, 2002 Sheet 2 of 25
1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK CPU PULL-UP / DOWN BLOCK
U13A
SDATA#0 AA35 AE1 A20M#
5 SDATA#[0..63] SDATA0 A20M A20M# 9
SDATA#1 W37 AG1 FERR# NMI 1 2 AIN#0 R101 680 PLBYCLK R65 100
SDATA1 FERR FERR# 9 VCORE VCORE VCORE
SDATA#2 W35 AJ3 CPUINIT# INTR 3 4 RN3 AIN#1 R95 680 R64 100
SDATA#3 SDATA2 INIT INTR CPUINIT# 9 SMI#
Y35 AL1 5 6 680
SDATA3 INTR INTR 9
SDATA#4 U35 AJ1 IGNNE# CPUINIT# 7 8 PLLMON1 R52 56 PLBYCLK# R57 100
SDATA4 IGNNE IGNNE# 9 VCORE
SDATA#5 U33 AN3 NMI PLLMON2 R44 56 R54 100
SDATA#6 SDATA5 NMI CPURST# NMI 9
S37 AG3
SDATA6 RESET CPURST# 5,9
SDATA#7 S33 AN5 SMI# STPCLK# 1 2 FLUSH# R20 680
SDATA7 SMI SMI# 9
SDATA#8 AA33 AC1 STPCLK# A20M# 3 4 RN6 PLLBP# R90 680
SDATA#9 SDATA8 STPCLK STPCLK# 9 IGNNE#
D AE37 5 6 680 VREFMODE R34 X_1K VCORE D
SDATA#10 AC33 SDATA9 AE3 R29 22 CPU_OK CPURST# 7 8 CPU_OK R31 270 R36 56.2RST
SDATA10 PWROK CPU_OK 20,21
SDATA#11 AC37 C49 X_10p
SDATA#12 Y37 SDATA11 PLLTEST# R15 510 FERR# R7 680
SDATA12 VREFMODE=Low=No voltage scaling
SDATA#13 AA37 N1 APICCLK_CPU DBREQ# R19 510
SDATA13 PICCLK N3 APICCLK_CPU 5 VCORE
SDATA#14 AC35 APICD0#
SDATA14 PICD0/BYPASSCLK N5 APICD0# 9
SDATA#15 S35 APICD1# RN12
SDATA#16 SDATA15 PICD1/BYPASSCLK APICD1# 9 CPU_TDI RN13
Q37 1 2
SDATA#17 Q35 SDATA16 AG13 COREFB# CPU_TRST# 3 4 SCANCLK2 1 2
SDATA#18 N37 SDATA17 COREFB- AG11 COREFB CPU_TCK 5 6 SSHIFTEN 3 4
SDATA#19 SDATA18 COREFB+ CPU_TMS SINTVAL
J33 7 8 5 6
SDATA#20 G33 SDATA19 AN17 CPUCLK_R SCANCLK1 7 8
SDATA#21 G37 SDATA20 CLKIN AL17 CPUCLK#_R 510
SDATA#22 E37 SDATA21 CLKIN 270
SDATA#23 SDATA22 FILVAL# R115 270
G35 AN19
SDATA#24 Q33 SDATA23 RSTCLK AL19 DOVAL# R109 270
SDATA#25 N33 SDATA24 RSTCLK
SDATA#26 SDATA25 CLKOUT
L33 AL21
SDATA#27 N35 SDATA26 K7CLKOUT AN21 CLKOUT#
SDATA#28 L37 SDATA27 K7CLKOUT
SDATA#29 SDATA28
J37
SDATA#30 A37 SDATA29 AJ13 C598 X_4.7u-0805(S/S) COREFB R42 10K
SDATA30 ANALOG VCORE VCORE
SDATA#31 E35
SDATA#32 E31 SDATA31 AA5 VREFMODE C600 4.7u-0805(S/S)
SDATA#33 SDATA32 SYSVREFMODE W5 VREF_SYS C601 X_4.7u-0805(S/S) COREFB# R48 0
E29
SDATA#34 A27 SDATA33 VREF_SYS
SDATA#35 A25 SDATA34 AC5 ZN
SDATA35 ZN AE5 Put in Solder
SDATA#36 E21 ZP
462-Pin Socket
SDATA#37 C23 SDATA36 ZP
C C
SDATA#38 C27 SDATA37 AJ25 PLLBP#
SDATA#39 SDATA38 PLLBYPASS AN15 PLBYCLK
A23
SDATA#40 A35 SDATA39 PLLBYPASSCLK AL15 PLBYCLK#
SDATA#41 C35 SDATA40 PLLBYPASSCLK
SDATA#42 C33 SDATA41 AN13 PLLMON1
SDATA42 PLLMON1 AL13
Part 1
SDATA#43 C31 PLLMON2
SDATA#44 A29 SDATA43 PLLMON2 AC3 PLLTEST# CPU SYSCLK BLOCK CPU Clock Multiplier CPU K7CLKOUT BLOCK
SDATA#45 C29 SDATA44 PLLTEST
SDATA#46 SDATA45
E23
SDATA#47 C25 SDATA46 S1 SCANCLK1 VCORE
SDATA#48 E17 SDATA47 SCANCLK1 S5 SCANCLK2
SDATA#49 SDATA48 SCANCLK2 S3 SINTVAL 5 CPUCLK CLKOUT R78 100
E13 VCORE
SDATA#50 E11 SDATA49 SCANINTEVAL Q5 SSHIFTEN FID2 1 2 R77 100
SDATA50 SCANSHIFTEN VCORE
SDATA#51 C15 CPUCLK_R C89 680p R67 X_60.4RST FID1 3 4 RN4
SDATA#52 E9 SDATA51 AA1 FID0 5 6 4.7K
SDATA#53 SDATA52 DBRDY AA3 DBREQ# FID3
A13 7 8
SDATA#54 C9 SDATA53 DBREQ AL3 FLUSH# R68 CLKOUT# R74 100
SDATA54 FLUSH VCORE
SDATA#55 A9 X_301RST R73 100
SDATA#56 SDATA55 CPU_TCK
C21 Q1
SDATA#57 A21 SDATA56 TCK U1 CPU_TDI CPUCLK#_R C105 680p R69 X_60.4RST
SDATA#58 E19 SDATA57 TDI U5
SDATA#59 SDATA58 TDO Q3 CPU_TMS CFID[3:0] => CPU Clock Multiplier
C19
SDATA#60 C17 SDATA59 TMS U3 CPU_TRST#
SDATA60 TRST 5 CPUCLK#
SDATA#61 A11
SDATA#62 A17 SDATA61 * Trace lengths of CLKOUT and
SDATA62
SDATA#63 A15 L1 VIDA0
VIDA[0..4] 11,22 CLOSE SOCKET4 62 CLKOUT# are between 2" and
SDATA63 VID0 L3 VIDA1
VID1 L5 VIDA2 3"
B
DICLK#0 VID2 VIDA3 B
W33 L7
5 DICLK#[0..3] SDATAINCLK0 VID3
DICLK#1 J35 J7 VIDA4
DICLK#2 E27 SDATAINCLK1 VID4
DICLK#3 SDATAINCLK2
E15
SDATAINCLK3 W1 FID0
FID0 FID[0..3] 5
AN33 W3 FID1
5 DIVAL# SDATAINVAL FID1 Y1 FID2 CPU SYSCLK REFERNCE BLOCK CPU ZN / ZP BLOCK CPU APIC BLOCK
DOCLK#0 FID2 FID3
AE35 Y3
5 DOCLK#[0..3] DOCLK#1 C37 SDATAOUTCLK0 FID3
DOCLK#2 A33 SDATAOUTCLK1 VCORE
DOCLK#3 C11 SDATAOUTCLK2 U37 VCC2_5
SDATAOUTCLK3 SCHECK0 Y33 ZN R39 40.2RST
SCHECK1 VCORE
DOVAL# AL31 L35 R50
SDTATOUTVAL SCHECK2 0.5 * VCORE 110RST ZP R38 56.2RST APICD0# R11 220
E33
AIN#0 AJ29 SCHECK3 E25 VREF_SYS
AIN#1 AL29 SADDIN0 SCHECK4 A31 APICD1# R13 220
AIN#2 AG33 SADDIN1 SCHECK5 C13 C64 C58 C59 R49
5 AIN#[2..14] AJ37 SADDIN2
AIN#3 SCHECK6 10u-0805 0.1u 0.047u 110RST APICCLK_CPU R174 X_453RST
A19 CLOSE SOCKET4 62
AIN#4 AL35 SADDIN3 SCHECK7
AIN#5 AE33 SADDIN4 J1
AJ35 SADDIN5
AIN#6 SADDOUT0 match the transmission line
J3
AIN#7 AG37 SADDIN6 SADDOUT1 C7 AOUT#2 CLOSE SOCKET4 62
AIN#8 AL33 SADDIN7 SADDOUT2 A7 AOUT#3 AOUT#[2..14] 5 Push-pull compensation circuit
AN37 SADDIN8
AIN#9 SADDOUT3 AOUT#4
E5
AIN#10 AL37 SADDIN9 SADDOUT4 A5 AOUT#5
AIN#11 AG35 SADDIN10 SADDOUT5 E7 AOUT#6
AIN#12 AN29 SADDIN11 SADDOUT6 C1 AOUT#7
AN35 SADDIN12
AIN#13 SADDOUT7 AOUT#8
C5
A AIN#14 AN31 SADDIN13 SADDOUT8 C3 AOUT#9 A
SADDIN14 SADDOUT9 G1 AOUT#10
SADDOUT10 AOUT#11
AJ33 E1
5 AICLK# SADDINCLK SADDOUT11 A3 AOUT#12
AJ21 SADDOUT12 G5 AOUT#13 MICRO-STAR INt'L CO., LTD.
5 CFWDRST AL23 CLKFWDRST SADDOUT13 G3 AOUT#14 MSI
5 CONNECT AN23 CONNECT SADDOUT14
5 PROCRDY FILVAL# AJ31 PROCRDY E3 Title
SFILLVAL SADDOUTCLK AOCLK# 5
N12-4620011-F02 AMD Socket462 CPU (Signal)
Size Document Number Rev
0B
**All CPU interface are 2.5V tolerant** (MS-6597)
Date: Tuesday, October 22, 2002 Sheet 3 of 25
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACE ONE CAP
CLOSE TO PIN M8
CPU VOLTAGE BLOCK
VCORE VCCA_PLL
0 ~ 100 mA (50mA)
2.25 ~ 2.75 V
AM34
AM30
AM26
AM22
AM18
AM14
AM10
AH26
AH22
AH18
AH14
AH10
AB30
AK36
AK34
AK30
AK26
AK22
AK18
AK14
AK10
AB36
AB34
AB32
AF14
AF18
AF22
AF26
AF36
AF34
AJ23
AM2
AH4
AH2
AD6
AD4
AD2
AC7
H12
H16
H20
H24
D32
D28
D24
D20
D16
D12
P30
X30
AL5
X36
X34
X32
P36
P34
P32
K36
K34
K32
B36
B32
B28
B24
B20
B16
B12
T30
T36
T34
T32
F36
F34
F32
F28
F24
F20
F16
F12
AJ5
M8
M4
M6
M2
R8
R6
R4
R2
H4
H2
D8
D4
D2
V8
V6
V4
V2
B8
B4
Z8
Z6
Z4
Z2
U13C
VCC_Z
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_CORE6
VCC_CORE7
VCC_CORE8
VCC_CORE9
VCC_CORE10
VCC_CORE11
VCC_CORE12
VCC_CORE13
VCC_CORE14
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VCC_CORE56
VCC_CORE57
VCC_CORE58
VCC_CORE59
VCC_CORE60
VCC_CORE61
VCC_CORE62
VCC_CORE63
VCC_CORE64
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VCC_CORE69
VCC_CORE70
VCC_CORE71
VCC_CORE72
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VCC_CORE89
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VCC_CORE94
VCC_CORE95
VCC_CORE96
VCC_CORE97
VCC_CORE98
VCC_CORE99
VCC_CORE100
VCC_CORE101
VCC_A
U13B AO1 YY24
N12-4620011-F02 AO2 GND GND YY23
GND GND
D AO3 YY22 D
AO4 GND GND YY21
AA31 GND GND YY20
NC1 AC31 GND YY19
NC2 GND
AD30 AE31 YY18
AD8 VCC_SRAM1 NC3 AG23 YY1 GND YY17
AF10 VCC_SRAM2 NC6 AG25 YY2 GND GND YY16
VCC_SRAM3 NC7 GND GND
AF28 AG31 YY3 YY15
AF30 VCC_SRAM4 NC8 AG5 YY4 GND GND YY14
AF32 VCC_SRAM5 NC9 AJ11 YY5 GND GND YY13
VCC_SRAM6 NC10 GND GND
AF6 AJ15 YY6 YY12
AF8 VCC_SRAM7 NC11 AJ17 YY7 GND GND YY11
AH30 VCC_SRAM8 NC12 AJ19 YY8 GND GND
AH8 VCC_SRAM9 NC13 AJ27 YY9 GND XX1
VCC_SRAM11 NC15 GND GND
AJ9 AL11 YY10 XX2
AK8 VCC_SRAM13 NC16 AN11 GND GND
AL9 VCC_SRAM14 NC17 AN9
VCC_SRAM16 NC18 N12-4620011-F02
AM8 G11
F30 VCC_SRAM17 NC19 G13
F8 VCC_SRAM19 NC20 G27
VCC_SRAM20 NC21
H10
VCC_SRAM21 NC22
G29 For 1.5GHz CPU Fan Holes
H28 G31
462-Pin Socket
H30 VCC_SRAM22 NC23 J31
H32 VCC_SRAM23 NC24 J5
VCC_SRAM24 NC25
H6 L31
H8 VCC_SRAM25 NC27 N31
Part 2
K30 VCC_SRAM26 NC28 Q31
VCC_SRAM27 NC29
K8 S31 THERMDP# 11
AJ7 VCC_SRAM28 NC30 S7
C C
AL7 VCC_SRAM29 NC31 U31 C24
VCC_SRAM30 NC32 X_1000p
AN7 U7 THERMDN# 11
VCC_SRAM31 NC33 W31
NC34 W7
NC35 Y31
NC36 Y5
NC37 AG19
G25 NC42 G21
KEY4 NC43
G17 AG21
G9 KEY6 NC44 G19
N7 KEY8 NC45
KEY10
Y7 AN27
AG7 KEY12 BP0_CUT AL27
AG15 KEY14 BP1_CUT AN25
AG29 KEY16 BP2_CUT AL25
KEY18 BP3_CUT
VCCA_PLL trace length from the regulator to
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