Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6712F1
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5 4 3 2 1
Title Page
MS-6712F1 Version 2.0B
11/04/2002 Update MS-6712F1 ver:2.0B Cover Sheet 1
VIA (R) KT400 VT8377 Chipset
Palamino/Mogan 462pin cPGA Processor Schematics Option L BOM (with LAN) Block Diagram 2
GPIO SPEC 3
D D
*AMD PGA 462 Processor SMT 5010 785
SMT 5020 19 AMD 462 PGA Socket 4,5
*VIA KT400 / VT8235 Chipset DIP 60 72
(DDR 400 / AGP 8X / VLink 8X) Clock Synthesizer 6
Total 878
*Winbond 83697HF-VF LPC I/O KT400 7,8,9,10
*VT6103 Fast Ethernet 10 / 100 Standard BOM (without LAN) System Memory 11,12,13
*AC'97 Codec ALC202A/ALC650 SMT 5010 XXX DDR Terminations 14
SMT 5020 XX
*USB 2.0 support (integrated into VT8235) DIP 60 XX
AGP SLOT 15
*Jump Less support Total XXX
VT8235 16,17,18
PCI Connectors 19,20
C C
CNR RISER / DLED 21
AC'97 Codec & Audio connector 22
ATA 66/100 Connectors 23
Ethernet LAN 24
Front USB Port & Rear USB Port 25
LPC I/O 26
H/W monitor;Fan; Thermal Protection 27
I/O Connectors 28
B B
HIP 6302 29
Orcad Config ERP BOM Function Description CPU Ratio / Vcore / LED Setting 30
MS-6712F1 20B With LAN. Without CNR.
6712F1-20B-L 601-6712-060 MSI Option:L MSI Standard MS-5 ACPI POWER 31
MS-6712F1 20B Without LAN.
MSI Standard MSI Standard Front Panel; PowerOK Circuit 32
BULK / Decoupling 33
HISTORY 34
A A
Micro Star Restricted Secret
Title Rev
Cover Sheet
20A
Document Number MS-6712
MICRO-STAR INT'L Last Revision Date:
CO.,LTD.
No. 69, Li-De St, Jung-He City, Friday, November 08, 2002
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 34
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Block Diagram
AMD Socket 462
D D
FSB200/266
A DDR 400
AGP 8X /Fast Write
G
C
P KT400 C
VLINK 8X
Dual ATA
PCI-33 100/133
6 PCI Slots
VT8235
B B
LPC BUS
MII 10/100M
Rear 10/100
Port x1 VT6103 PHY
SUPER I/O ROM
USB 2.0
C
N
AC-LINK
R
X BUS
AC'97 Codec
A A
Dual USB 1.1 OHCI
/2.0 EHCI 6 Ports
Micro Star Restricted Secret
Title Rev
Block Diagram
Rear x2 Front x4 Document Number MS-6712
20A
MICRO-STAR INT'L Last Revision Date:
CO.,LTD.
No. 69, Li-De St, Jung-He City, Friday, November 08, 2002
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 2 of 34
5 4 3 2 1
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GPIO FUNCTION
VT8233 GPIO Function Define
PIN NAME Function define PIN NAME Function define
D D
GPO0 (VSUS33) GPO0 GPI0 GPI0
GPO1/SUSA#(VSUS33) SUSA# GPI1 ATADET0=>Detect IDE1 ATA100/66
GPO2/SUSB#(VSUS33) SUSB# GPI2/EXTSMI# EXTSMI#
GPO3/SUSST1#(VSUS33) SUSST1# GPI3/RING# RING#
GPO4/SUSCLK(VSUS33) SUSCLK GPI4/LID# ATADET1=>Detect IDE2 ATA100/66
GPO5/CPUSTP# CPUSTP# GPI5/BATLOW# Exteranl Pull up to 3VDUAL
GPO6/PCISTP# PCISTP# GPI6/PME# PME#
GPO7/SLP# SLP# GPI7/SMBALRT# Exteranl Pull up to 3VDUAL PCI
GPO8/GPI8/IPBIN0 Exteranl Pull up to VCC3 GPI16/INTRUDER# Exteranl Pull down DEVICES INT# IDSEL REQ#/GNT# CLOCK
GPO9/GPI9/IPBIN1 Exteranl Pull up to VCC3 GPI17/CPUMISS Exteranl Pull up to 3VDUAL INT#A PREQ#1
C PCI SLOT 1 INT#B AD16 PCICLK1 C
INT#C PGNT#1
GPO10/GPI10/IPBRDFR GPI10(PRI_DOWN) GPI18/AOLGP1/THRM# THRM# INT#D
GPO11/GPI11/IPBRDCK GPI19/IORDY Exteranl Pull up to VCC3 INT#B PREQ#2
PCI SLOT 2 INT#C AD17 PCICLK2
INT#D PGNT#2
GPO12/GPI12/IPBOUT0 GPO12 INT#A
DDR Voltage SET1 SET2
GPO13/GPI13/IPBOUT1 GPO13 INT#C PREQ#3
PCI SLOT 3 INT#D AD18 PCICLK3
2.5V 1 1 INT#A PGNT#3
GPO14/GPI14/IPBTDFR GPO14 INT#B
2.6V 0 1
GPO15/GPI15/IPBTDCK GPO15 2.7V 1 0 INT#D PREQ#4
PCI SLOT 4 INT#A AD19 PCICLK4
2.8V 0 0 INT#B PGNT#4
GPO16/SA16/STRAP CPU FID0 Strapping INT#C
GPO17/SA17/STRAP CPU FID1 Strapping INT#B PREQ#5
PCI SLOT 5 INT#C AD21 PCICLK5
INT#D PGNT#6
GPO18/SA18/STRAP CPU FID2 Strapping INT#A
B GPO19/SA19/STRAP CPU FID3 Strapping INT#C PREQ#0 B
PCI SLOT 6 INT#D PCICLK6
GPO20/GPI20 INT#A AD22 PGNT#0
/ACSDIN2/PCS0#/EI GPO20 INT#B
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN# GPO21
GPO22/GPI22/IOR# GPO22
GPO23/GPI23/IOW# GPO23
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2
(VSUS33) SMBDATA2/Slave SMBUS
GPO27/GPI27/SMBCK2
(VSUS33) SMBCLK2/Slave SMBUS
GPO28/GPI28/
APICD0/APICCS#
GPO29/GPI29/
A APICD1/APICACK# A
GPO30/GPI30/GPIOD
Micro Star Restricted Secret
GPO31/GPI31/GPIOE Title Rev
GPIO Spec. 20A
Document Number MS-6712
MICRO-STAR INT'L Last Revision Date:
CO.,LTD.
No. 69, Li-De St, Jung-He City, Friday, November 08, 2002
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 34
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SOCKET 462 Part 1
**All CPU interface are 2.5V tolerant**
VCORE
VCC3
CPU1A
SDATA#[0..63] SDATA#0 AA35 AE1 A20M# CPURST# VCORE DBREQ# R87 510
{7} SDATA#[0..63] SDATA0 A20M A20M# {16}
SDATA#1 W37 AG1 FERR
SDATA#2 SDATA1 FERR CPUINIT#
W35 SDATA2 INIT AJ3 CPUINIT# {16} R7
SDATA#3 Y35 AL1 INTR C10 510
SDATA#4 SDATA3 INTR IGNNE# INTR {16} PLLTEST# R98 510
U35 SDATA4 IGNNE AJ1 X_100P R12
SDATA#5 NMI IGNNE# {16}
U33 SDATA5 NMI AN3 680
SDATA#6 CPURST# NMI {16}
S37 SDATA6 RESET AG3
SDATA#7 SMI# CPURST# {30} FERR# CPU_TCK
D
S33 SDATA7 SMI AN5 SMI# {16} FERR# {16} 7 8 D
SDATA#8 AA33 AC1 STPCLK# CPU_TMS 5 6
C
SDATA#9 SDATA8 STPCLK STPCLK# {16} CPU_TRST#
AE37 SDATA9 3 4
SDATA#10 AC33 AE3 FERR B Q5 CPU_TDI 1 2
SDATA#11 SDATA10 PWROK K7PWRGD {30}
AC37 2N3904S
SDATA#12 SDATA11 RN5
Y37 SDATA12
SDATA#13
E
AA37 N1 APICCLK_CPU 8P4R-510
SDATA#14 SDATA13 PICCLK APICCLK_CPU {6} VCORE
AC35 N3 APICD0#
SDATA#15 SDATA14 PICD0/BYPASSCLK APICD1# APICD0# {16}
S35 SDATA15 PICD1/BYPASSCLK N5 APICD1# {16}
SDATA#16 Q37
SDATA#17 SDATA16 COREFB#
Q35 SDATA17 COREFB- AG13 COREFB# {29}
SDATA#18 N37 AG11 COREFB R74
SDATA#19 SDATA18 COREFB+ COREFB {29} for test only
J33 SDATA19 60.4RST
SDATA#20 G33 AN17 CPUCLK_R VCC2_5 0.6 * VCORE
SDATA#21 SDATA20 CLKIN CPUCLK#_R
SDATA#22
G37 SDATA21 CLKIN AL17 Pull to 2.5V
E37 VREF_SYS
SDATA#23 SDATA22
G35 SDATA23 RSTCLK AN19
SDATA#24 Q33 AL19 APICD0# R22 330
SDATA#25 SDATA24 RSTCLK APICD1# R17 330
N33 SDATA25 C43 C42 R73
SDATA#26 L33 AL21 CLKOUT 473P 473P 60.4RST
SDATA#27 SDATA26 K7CLKOUT CLKOUT#
N35 SDATA27 K7CLKOUT AN21
SDATA#28 L37 C35
SDATA#29 SDATA28 VCORE
J37 SDATA29 X_39P
SDATA#30 A37 AJ13
SDATA#31 SDATA30 ANALOG
E35 SDATA31
SDATA#32 E31 AA5 VREFMODE
SDATA#33 SDATA32 SYSVREFMODE VREF_SYS
E29 SDATA33 VREF_SYS W5
SDATA#34 A27 R78 R82 VCORE
SDATA34 {6} CPUCLK
SDATA#35 A25 AC5 ZN 100 100
SDATA#36 SDATA35 ZN ZP C63
E21 SDATA36 ZP AE5
C SDATA#37 C23 VCORE CPUCLK_R R85 60.4RST C
SDATA#38 SDATA37 PLLBP#
C27 SDATA38 PLLBYPASS AJ25
SDATA#39 A23 AN15 680P
SDATA#40 SDATA39 PLLBYPASSCLK COREFB R54 10K
A35 SDATA40 PLLBYPASSCLK AL15
SDATA#41 C35 R90
SDATA#42 SDATA41 PLLMON1
C33 SDATA42 PLLMON1 AN13 C34 301RST
SDATA#43 C31 AL13 PLLMON2
SDATA#44 SDATA43 PLLMON2 PLLTEST# X_106P/0805
A29 SDATA44 PLLTEST AC3 R79 R83
SDATA#45 C29 100 100 COREFB# R63 10K C65
SDATA#46 SDATA45 CPUCLK#_R R93 60.4RST
E23 SDATA46
SDATA#47 C25 S1 SCANCLK1
SDATA#48 SDATA47 SCANCLK1 SCANCLK2 680P
SDATA#49
E17 SDATA48 SCANCLK2 S5
SINTVAL
close Socket 462
E13 SDATA49 SCANINTEVAL S3 {6} CPUCLK#
SDATA#50 E11 Q5 SSHIFTEN
SDATA#51 SDATA50 SCANSHIFTEN
C15 SDATA51
SDATA#52 E9 AA1
SDATA#53 SDATA52 DBRDY DBREQ# VCORE
A13 SDATA53 DBREQ AA3
SDATA#54 C9 AL3 FLUSH# VCORE
SDATA#55 SDATA54 FLUSH RN8
A9 SDATA55
SDATA#56 C21 Q1 CPU_TCK IGNNE# 1 2
SDATA#57 SDATA56 TCK CPU_TDI A20M#
A21 SDATA57 TDI U1 3 4 R92
SDATA#58 E19 U5 STPCLK# 5 6 for internal
SDATA#59 SDATA58 TDO CPU_TMS CPURST# X_1K
C19 SDATA59 TMS Q3 7 8 VREFSYS
SDATA#60 C17 U3 CPU_TRST#
SDATA#61 SDATA60 TRST 8P4R-680 VREFMODE
A11 SDATA61
SDATA#62 A17
SDATA#63 SDATA62 VID0 RN11
A15 SDATA63 VID0 L1 VID0 {29}
L3 VID1 SMI# 1 2 R91
VID1 VID1 {29}
L5 VID2 NMI 3 4 270
VID2 VID2 {29}
DICLK#[0..3] DICLK#0 W33 L7 VID3 CPUINIT# 5 6
B {7} DICLK#[0..3] DICLK#1 SDATAINCLK0 VID3 VID3 {29} B
J35 J7 VID4 INTR 7 8
DICLK#2 SDATAINCLK1 VID4 VID4 {29}
E27 SDATAINCLK2
DICLK#3 E15 8P4R-680
SDATAINCLK3 FID0
DIVAL# FID0 W1
FID1 FID0 {5} FLUSH# R50 680
VREFMODE=Low=No voltage scaling
{7} DIVAL# AN33 SDATAINVAL FID1 W3 FID1 {5}
Y1 FID2 PLLBP# R103 680
DOCLK#0 FID2 FID2 {5}
{7} DOCLK#[0..3] DOCLK#[0..3] AE35 Y3 FID3
DOCLK#1 SDATAOUTCLK0 FID3 FID3 {5} PLLMON1 VCORE
C37 R77 56
DOCLK#2 SDATAOUTCLK1 PLLMON2 R76 56
A33 SDATAOUTCLK2
DOCLK#3 C11 U37 ZN R97 40.2RST
SDATAOUTCLK3 SCHECK0 RN29
SCHECK1 Y33
DOVAL# AL31 L35 DOVAL# 1 2 ZP R88 40.2RST
SDTATOUTVAL SCHECK2 FILVAL#
SCHECK3 E33 3 4
AIN#0 AJ29 E25 AIN#1 5 6
AIN#1 SADDIN0 SCHECK4 AIN#0
AL29 SADDIN1 SCHECK5 A31 7 8 match the transmission line
{7} AIN#[2..14] AIN#[2..14] AIN#2 AG33 C13 Push-pull compensation circuit
AIN#3 SADDIN2 SCHECK6 8P4R-270
AJ37 SADDIN3 SCHECK7 A19
AIN#4 AL35
AIN#5 SADDIN4 RN6
AE33 SADDIN5 SADDOUT0 J1
AIN#6 AJ35 J3 SCANCLK2 1 2 VCORE
AIN#7 SADDIN6 SADDOUT1 AOUT#2 AOUT#[2..14] SCANCLK1 RN25
AG37 SADDIN7 SADDOUT2 C7 AOUT#[2..14] {7} 3 4
AIN#8 AL33 A7 AOUT#3 SINTVAL 5 6 1 2
AIN#9 SADDIN8 SADDOUT3 AOUT#4 SSHIFTEN CLKOUT
AN37 SADDIN9 SADDOUT4 E5 7 8 3 4
AIN#10 AL37 A5 AOUT#5 CLKOUT# 5 6
AIN#11 SADDIN10 SADDOUT5 AOUT#6
AG35 SADDIN11 SADDOUT6 E7 8P4R-270 7 8
AIN#12 AN29 C1 AOUT#7
AIN#13 SADDIN12 SADDOUT7 AOUT#8 8P4R-100
AN35 SADDIN13 SADDOUT8 C5
AIN#14 AN31 C3 AOUT#9 * Trace lengths of CLKOUT
SADDIN14 SADDOUT9 AOUT#10
G1
A {7} AICLK# AJ33
SADDOUT10
E1 AOUT#11 and -CLKOUT are between A
SADDINCLK SADDOUT11 AOUT#12
SADDOUT12 A3 2" and 3"
CFWDRST AJ21 G5 AOUT#13
{7} CFWDRST CONNECT CLKFWDRST SADDOUT13
AL23 G3 AOUT#14
{7} CONNECT CONNECT SADDOUT14
PROCDRY AN23 Micro Star Restricted Secret
{7} PROCDRY PROCRDY
FILVAL# AJ31 E3
SFILLVAL SADDOUTCLK AOCLK# {7}
Title Rev
N12-4620011-F02 SOCKET 462 Part 1 20A
Document Number MS-6712
MICRO-STAR INT'L Last Revision Date:
CO.,LTD.
No. 69, Li-De St, Jung-He City, Friday, November 08, 2002
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 4 of 34
5 4 3 2 1
A
B
C
D
100mA
3VDUAL
{6} 166_DET
spec.
change
C30
104P
Design for
Max 150mA,
Used when
3VDUAL
X_1K
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