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                                 AMD Engineering - Internal Use Only - October 4, 2004 9:55 am




AMD GeodeTM GX Processors
Intermittent Screen Tearing
Issue Resolution

1.0        Scope                                                         2.0         Discussion
This document provides a programming resolution for an                   During testing of the Geode GX processors, some devices
Intermittent graphics issue observed with the AMD                        exhibited a tearing in the rendered display. The pro-
GeodeTM GX processor (i.e., Geode GX [email protected] pro-                       grammed value in the RAM Control MSR (MSR Address
cessor*, Geode GX [email protected] processor*, and Geode GX                      80002012h) bits [26:24] and [18:16] were found to be the
[email protected] processor*).                                                    cause of this issue. (See Table 2-1 for bit descriptions.)
                                                                         The default BIOS value of 4h (100b) is incorrect and needs
                                                                         to be changed to 6h (110b). The full value of this register
                                                                         should be changed in the BIOS from 04040202h to
                                                                         06060202h. Additional testing with the new value corrected
                                                                         the observed problem.


                                         Table 2-1. MSR_RAM_CTL Bit Descriptions
    Bit       Name                   Description

   63:27      RSVD                   Reserved. Write as read.
   26:24      DFIFO_CTL1             DFIFO RAM 1 Delay Control. This bit determines the precharge delay for the DFIFO1
                                     DFIFO0, CFIFO, or DV] RAM cell. (Recommended setting: 110.)
   23:19      RSVD                   Reserved. Write as read.
   18:16      DFIFO_CTL0             DFIFO RAM 0 Delay Control. This bit determines the precharge delay for the DFIFO0
                                     RAM cell. (Recommended setting: 110.)
   15:11      RSVD                   Reserved. Write as read.
   10:8       CFIFO_CTL              CFIFO RAM Delay Control. This bit determines the precharge delay for the CFIFO RAM
                                     cell.
    7:3       RSVD                   Reserved. Write as read.
    2:0       DV_RAM_CTL             DV RAM Delay Control. This bit determines the precharge delay for the DV RAM cell.




*The AMD Geode GX [email protected] processor operates at 400 MHz, the AMD Geode GX [email protected] operates at 366 MHz, and the AMD Geode GX [email protected]
processor operates at 333 MHz. Model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodegxbenchmark.

32494A - October 2004 - Confidential                                                                                                         1
                                    AMD Engineering - Internal Use Only - October 4, 2004 9:55 am




                                     

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