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gx_5530a_schema_cklst


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AMD GeodeTM GX1 Processor/
CS5530A Companion Device
Schematic Checklist

1.0       Scope
AMD GeodeTM Solutions offer custom products for the          2.1        GX1 Processor
information appliance market. This schematic review
                                                             1)    Bypass and pull-up components on SDCLK lines at
checklist was developed to assist FAEs and OEMs in their
                                                                   the DIMMs should be no-loads if they are there at all.
schematic design and review process when using the AMD
GeodeTM GX1 processor and AMD GeodeTM CS5530A                2)    Verify that the SDCLK lines and SDCLK_OUT 
companion device.                                                  SDCLK_IN loop adhere to the current layout guide-
                                                                   lines for the processor being used.
Note:   This is revision 1.2 of this document. The differ-
        ence from revision 1.1 (dated October 2000) is the   3)    Make sure SMI# is pulled up.
        addition of item 2 in Section 2.5 "MK1491 Clock
                                                             4)    10 ohm series termination resistors are required on
        Generator" on page 3 regarding spread spectrum
                                                                   the MA bus, MD bus, and memory control lines. The
        support.
                                                                   resistors should be placed close to the processor.
                                                             5)    Make sure TEST is pulled down.
2.0       Discussion                                         6)    Make sure FLT# is pulled up with a 10 K-ohm resistor.
The following subsections describe the critical device and
interface connections for the GX1 processor and CS5530A      7)    Make sure 10K pull-ups are on all the processor's
companion device and National Semiconductor's PC97317              REQ# and GNT# lines.
SuperI/O and DP83815 MacPHYTER devices.                      8)    MICTOR connectors should be included in the design
                                                                   to provide access to the PCI bus for debug. Refer to
                                                                   the AMD GeodeTM Processor PCI Access Header
                                                                   application note.
                                                             9)    Be sure not to significantly imbalance the memory
                                                                   controller. An example of this situation would be a sys-
                                                                   tem with four pieces of SDRAM using CS0#, RAS0#,
                                                                   CAS0#, etc. and a DIMM socket using CS2# and
                                                                   CS3#, RAS1#, CAS1#, etc. Since a DIMM can have
                                                                   16 or more pieces of SDRAM and the other half of the
                                                                   interface only has four, setup and hold times will vary
                                                                   significantly between the two halves and will likely
                                                                   cause one of them to fail.
                                                             10) Ensure the GX1 processor's core voltage is bulk
                                                                 decoupled with four 100 



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