Service Manuals, User Guides, Schematic Diagrams or docs for : Agilent 5989-6841EN Physical Layer Test System (PLTS) 2014 - Technical Overview c20140919 [26]

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Keysight Technologies
Physical Layer Test System
(PLTS) 2014

Technical Overview

Vector Network Analyzer-based and
Time Domain Reflectometer-based Systems
Includes "What's New in PLTS 2014 Software
What's New with PLTS 2014?

The new Physical Layer Test System (PLTS) 2014 includes The 1-port automatic fixture removal tool is a breakthrough
novel features that will help solve real world problems extension of the 2X THRU AFR that saves the user from
for today's signal integrity engineers. There are so many designing and fabricating special calibration structures on
signal integrity tools available for design, analysis, and PCBs. Now, the test fixture itself can be used as the "1X
troubleshooting of high-speed interconnects it's difficult THRU" structure with an open circuit on port 2. This is
to manage them all. The Keysight Technologies, Inc. PLTS extremely helpful when working with FPGA applications
design team has created version 2014, integrating new where it is nearly impossible to create a normal 2X THRU
features into PLTS for a substantial boost in productivity. structure. Furthermore, the accuracy can be enhanced by
using additional calibration structures together such as an
PLTS is the signal integrity industry solution for open, short and/or THRU. This error correction flexibility
measurement and analysis of physical layer devices. gives the signal integrity engineer more control over
Wizards help users to calibrate and measure multiport accuracy versus ease-of-use decisions that need to be
devices with ease. Once measured, PLTS has a rich set of made for leading edge applications.
displays, analysis, data reformatting and conversion tools,
as well as a versatile set of import and export capabilities.
PLTS works with PNA and ENA network analyzers, and
TDRs. Data and transmission line models can be exported
to, or imported from simulation tools. The analysis features
include single-ended and differential plots in frequency or
time, as well as eye diagrams and RCLG model extraction.

Major tool advancements
Many usability features have been incorporated into
PLTS 2014, but there are two new capabilities that are
considered breakthrough for the technical industry. The
first is multi-channel simulation (Figure 1) and the other is
1-port automatic fixture removal (AFR)(Figure 2). Together
they create a time saving tool that helps the experienced Figure 1. Multi-channel simulation capability allows users to quickly measure
user accomplish more advanced analysis of the physical a channel, remove any fixtures, and then simulate the measured channels'
layer channel. performance using the newly added capability to use vendor supplied IBIS-AMI
models for TX and RX.
The multi-channel simulation capability allows the user to
quickly measure a channel, remove any fixtures and then
simulate the measured channels' performance. The newly
added capability to use vendor supplied IBIS-AMI models
for TX and RX creates real-world simulation results.

Built-in TX sources can be customized to match a
specified signal. Users can specify data rates, lengths
and voltages and then add noise, jitter, and pre-emphasis.
The built-in customizable RX allows the user to select
from the common CTLE, FFE, and DFE equalizers. Multiple
sources can be added to simulate aggressor cross talk for
multi-channel simulations. The resulting waveforms can be
displayed in multi-color eye diagrams with histograms for
common eye measurements.

Figure 2. 1-port AFR wizard provides more control of error correction techniques
by enabling the test fixture itself to be used as the calibration standard rather than
requiring the additional "2X THRU" structure to be fabricated.
2
Why is Physical Layer Testing Required?

The next generation computer and communication In order to maintain signal integrity throughout the
systems now being developed will handle data rates of complete channel, engineers are moving away from
multiple gigabits/second. Many systems will incorporate single-ended circuits and now use differential circuits. The
processors and SERDES chip sets that exceed GigaHertz differential circuit provides good Common Mode Rejection
clock frequencies. New and troubling input/output issues Ratio (CMRR) and helps shield adjacent PCB traces from
are emerging as switches, routers, server blades, and crosstalk. Properly designed differential transmission lines
storage area networking equipment moving toward will minimize the undesirable effect of mode conversion
10 Gbps data rates. Digital design engineers choosing and enhance the maximum data rate throughput possible.
chip-to-chip and backplane technologies for these systems Unfortunately, differential signaling technology is not
are finding signal integrity challenges that have not been always an intuitive science.
encountered before.
Differential transmission lines coupled with the microwave
Traditional parallel bus topologies are running out effects of high-speed data have created the need for
of bandwidth. As parallel busses become wider, the new design and validation tools for the digital design
complexity and cost to route on PC boards increase engineer. Understanding the fundamental properties
dramatically. The growing skew between data and clock of signal propagation through measurement and post-
lines has become increasingly difficult to resolve within measurement analysis is mandatory for today's leading
parallel busses. The solution is fast serial channels. The edge telecommunication and computer systems. The
newer serial bus structure is quickly replacing the parallel traditional Time Domain Reflectometer (TDR) is still a very
bus structure for high-speed digital systems. Engineers useful tool, but many times the Vector Network Analyzer
have been turning to a multitude of gigabit serial (VNA) is needed for the complete characterization of
interconnect protocols with embedded clocking to achieve physical layer components. There is a strong need for
the goal of simple routing and more bandwidth per pin. a test and measurement system that will allow simple
However, these serial interconnects bring their own set of characterization of complex microwave behavior seen
problems. in high speed digital interconnects. In fact, many digital
standards groups have now recognized the importance of
In order to maintain the same total bandwidth as the specifying frequency domain physical layer measurements
older parallel bus, the new serial bus needs to increase as a compliance requirement. Both Serial ATA and PCI
its data rate. As the data rate increases through serial Express have adopted the SDD21 parameter (input
interconnects, the rise time of the data transition from a differential insertion loss) as a required measurement to
zero logic level to a one logic level becomes shorter. This ensure channel compliance (Figure 3). This parameter
shorter rise time creates larger reflections at impedance is an indication of the frequency response that the
discontinuities and degrade the eye diagram at the end of differential signal sees as it propagates through the high-
the channel. As a result, physical layer components such speed serial channel. An example of a proposed SDD21
as printed circuit board traces, connectors, cables, and IC compliance mask is shown in Figure 5 for the Channel
packages can no longer be ignored. In fact, in many cases, Electrical Interface (CEI) working group for the Optical
the silicon is so fast that the physical layer device has Internetworking Forum (OIF).
become the bottleneck.
0
SDD21 (dB)

ISI Loss > 4 dB

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