Service Manuals, User Guides, Schematic Diagrams or docs for : Agilent 5990-9111EN Simulating High-Speed Serial Channels with IBIS-AMI Models c20140829 [19]
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
![5990-9111EN Simulating High-Speed Serial Channels with IBIS-AMI Models c20140829 [19]](/pics/5c4d6c5004523.gif)
>> Download 5990-9111EN Simulating High-Speed Serial Channels with IBIS-AMI Models c20140829 [19] documenatation <<
Text preview - extract from the document
Keysight Technologies
Simulating High-Speed Serial
Channels with IBIS-AMI Models
Bob Sullivan, Michael Rose, Jason Boh
Application Note
Introduction
The Input/Output Buffer Information Specification (IBIS) has been an essential component of the electrical
simulation toolbox for nearly two decades. Many design engineers are familiar with the application of IBIS
models and for the most part, the models have provided an accurate, easy-to-use alternative to SPICE-based
transistor models. In fact, most IBIS models are simple behavioral translations of a vendor's SPICE buffer
model. However, as serial interface bit rates increase, critical limitations with IBIS models have become more
acute.
With the current (version 5.0) of the IBIS specification, an important algorithmic modeling component has
been added to the conventional behavioral analog IBIS model. Several earlier efforts were made to add a
mixed-signal model capability with limited success. IBIS-Algorithmic Modeling Interface (AMI) represents an
important milestone in the IBIS mixed-signal evolution.
This paper reviews some of the benefits and limitations of using IBIS models and introduces the new AMI
extensions to the latest IBIS version 5.0 specification. Additionally, it illustrates how to perform several
simulations of a typical backplane system using the Advanced Design System 2011 (ADS2011) toolset.
IBIS Historical Perspective
The first version of IBIS was released in 1993 through the IBIS Open Forum. There
are many reasons for the popularity of IBIS models; namely, that they are widely
available, standardized (ANSI/EIA-656 and GEIA-STD-0001), and the specification
is controlled by an open forum with a membership of top tier EDA and silicon
vendors and equipment manufacturers. Since IBIS models are behavioral, simula-
tion times are usually very fast and do not suffer from convergence issues. Unlike
un-encrypted SPICE transistor-level circuit models, IBIS models do not expose the
intellectual property (IP) of the silicon vendor or foundry. In addition, transistor-
level models are generally encrypted for a single specific EDA tool. In contrast,
IBIS models are portable allowing them to run on any EDA tool that supports the
standard. IC vendors are not burdened with generating and supporting one model
for each EDA tool. And, integration support for IBIS is excellent. Moreover, there
are a number of free utilities for viewing, translating and parsing IBIS models.
IBIS models can support most IO buffer types and signaling standards through a
table of I-V and V-t curves for both transistors in the complimentary pair of a buffer.
Rising and falling edges are characterized in separate tables. The I-V curves provide
the steady state characteristics, while the V-t curves modify the buffer's behavior
for transient conditions. Together, these tables capture the fundamental buffer
characteristics including nonlinearity behaviors. As shown in Figure 1, the basic
IBIS electrical model is able to characterize the output buffer including the clamp
diodes, the die capacitance and the lumped package parasitics.
Figure 1. A basic IBIS input and output
buffer model schematic.
3
The power pins also include package parasitics that help model simultaneous
switch noise. Additional keywords can be used to characterize behaviors such
as slew-rate with the [Ramp] keyword and the [Vmeas], [Vref], [Rref], & [Cref]
keywords for modeling Tco loading characteristics.
IBIS models do have some inherent limitations. For instance, they do not include
any internal timing information for calculating input to output propagation
delays. Also, the simple lumped element package model (shown in Figure 1
as L_pkg, R_pkg, and C_pkg) only includes the self impedance and not mutual
impedance. Later versions of IBIS had a mechanism for including an external
".pkg" file for defining RLGC impedance matrices. Some silicon vendors provide
package models in this format, although broadband S-parameter package mod-
els are typically used for high-speed serial analysis. Generally speaking, early
IBIS models were unable to simulate crosstalk in IC packages. Later versions
of IBIS provided a simple mechanism for including the effects of simultaneous
switching output (SSO) and ground bounce through the [Pin Mapping] func-
tion used to associate specific signal and power pins. Starting with IBIS 4.0,
the C_Comp value can be split into separate components for Pullup, Pulldown,
POWER Clamp, and GND Clamp, which improves power integrity simulation
capabilities.
Another set of limitations involves the C_comp element shown in Figure 1.
This capacitor is intended to represent the buffer's die capacitance. However,
die capacitance has both a frequency and voltage dependence that cannot
be accurately represented with a single, fixed C_comp value. Also, there is a
problem with the C_comp implementation that involves the way differential
buffers are constructed with two single-ended buffers associated through the
[Diff Pin] keyword. While the C_comp component can reasonably model the
common-mode capacitance in differential configurations, it does not model the
differential mode capacitance that can lead to AC errors. Another common type
of error involving C_comp occurs if the loading capacitance is not considered in
the [ramp] V-t curves.
Another limitation became apparent as interest grew in adding pre-emphasis
to IBIS transmitter models. The C_comp value is usually extracted and treated
as an external capacitor element in EDA tools and therefore cannot be adjusted
on-the-fly when a model uses IBIS [Driver Scheduling] to switch between the
normal and boosted buffer outputs.
4
Introducing IBIS-AMI
As the complexity of high-speed serial channels continues to evolve, a new
simulation methodology has emerged to manage the ballooning simulation
run times. With bit times dropping down to the picoseconds range, classic
time-domain transient simulations that iteratively solve a set of simultaneous
equations are no longer practical due to the extremely long simulation time and
the expanding transistor count associated with the complex digital equalization
blocks. IBIS-AMI addresses this problem by supporting both time-domain super-
position (quasi-analytic or bit-by-bit mode) and statistical mode. These relatively
new simulation techniques offer orders-of-magnitude improvement in simulation
run time while preserving the accuracy of transient convolution simulation. IBIS-
AMI still performs a transient convolution of the channel's differential mode
impulse response initially. This step is accomplished in a much shorter period
(on the order of 20 to 30 unit intervals, depending on the settling time of the
analog channel). From that point on, solutions are provided by signal processing
functions that execute much faster than transient convolution solvers. These
methods are contrasted in greater detail later in this paper and in several refer-
ences cited at the end.
At the same time, designers face a new challenge characterizing the complex
digital signal processing functions found in multi-Gbps transceivers such as
equalization and clock data recovery (CDR). Very high bit rates typically require
sophisticated equalization techniques to cancel out a channel's attenuation
and dispersion losses and must be accounted for if the simulation is to have
meaningful results.
The arrangement of a typical high-speed serial interface is shown in Figure 2.
On the transmit side, the data stream is serialized, encoded and fed to the DSP.
Likewise, at the receiver, the stream is de-serialized and decoded before being
buffered. DSP signal processing filtering blocks are used to implement functions
such as Feed-Forward Equalization (FFE) and Decision Feedback Equalization
(DFE), Clock Data Recovery (CDR), and bit slicing. The analog sections contain
the behavioral buffer descriptions, as well other important analog functions such
as package parasitics, and for some transceivers, a linear equalizer stage. The
transceiver's analog buffers along with the physical channel form the "analog
channel model," which is characterized together with the impulse response
transient simulation.
Figure 2. IBIS-AMI model partitioning.
5
SerDes designers have often used various combinations of custom and off-
the-shelf mixed-signal modeling tools such as MATLAB, Verilog-AMS and
VHDL-AMS to co-simulate the digital and analog sections of their transceivers.
IC vendors are understandably reluctant to release the algorithmic code used
to implement the digital pieces since it contains valuable IP. A system engineer
interested in the overall channel behavior would have to model the transceivers
behaviorally using generic macro models or create custom algorithmic functions
in a tool such as MATLAB or the Keysight Technologies, Inc. Ptolemy. Without
specific knowledge of a particular transceiver design, this task is difficult at
best. Several SerDes vendors, such as IBM with its HSSCDR MATLAB-based
simulator, provide models embedded and distributed with its proprietary simula-
tor tool. Unfortunately though, this tool is not interoperable between IC or EDA
tool vendors.
The IBIS 5.0 AMI models the functions typically implemented in the DSP block
at a behavioral level. Unlike other mixed-signal modeling formats though, the IP
is hidden and protected within a compiled executable that is called by the EDA
tool through a standardized interface. The algorithmic code is provided as an
executable DLL Dynamic Link Library (DLL) file for Windows-based PCs or an
Shared Object (SO) file for Linux systems.
IBIS-AMI Simulation Requirements
The simulation methods used in IBIS-AMI 5.0 depend on the assumption that
the analog channel is both linear and time invariant. The Linear and Time
Invariant (LTI) premise allows accurate and efficient conversion between the
channel's impulse response and frequency response through the fast Fourier
transform (FFT). Likewise, the input to output transfer function may be derived
from the impulse response through the convolution process y(t) = x(t) * h(t). The
transmit bit stream is conditioned by the convolved impulse response to predict
the signal at the receiver. The resultant Rx waveform is then used to develop
the eye opening contours using superposition.
While the passive interconnect elements within a channel are typically LTI, the
IBIS Tx buffer tables can have nonlinear characteristics. CMOS buffers often
have time variations in impedance as well. Tx equalization tap settings may
also impact the buffer's linearity. Even though IBIS specifies the LTI require-
ment, it cannot be simply assumed and testing is needed to gain confidence
in the simulation results. Methods for handling nonlinear, time-variant (NLTV)
buffer behavior are currently being discussed in the IBIS Advanced Technology
Modeling Task Group (e.g., for the purpose of modeling mid-channel repeater
chips like re-drivers and re-timers, and optoelectronic links).
6
Simulation Flow
To understand the capabilities and limitations of IBIS-AMI models, it is impor-
tant to understand how IBIS-AMI models interact with the simulation tool.
IBIS-AMI supports two primary simulation flow methodologies: one for time-
domain simulation using a superposition (or "bit-by-bit") technique and another
for statistic simulation. Although the two methods have similar performance and
accuracy, they also have unique limitations. For instance, the algorithmic model
may support NLTV equalization behaviors for time-domain simulation, whereas
statistic simulations require LTI equalization modeling. Also, in some EDA tools,
jitter modeling is implemented differently for statistical simulation. For time-
domain simulations, Tx jitter is added to the stimulus waveform. For statistical
simulation, Tx jitter may be post-processed at the receiver output by some EDA
platforms.
(Note that ADS applies the same Tx jitter treatment in time domain and statisti-
cal modes. Adding Tx jitter in post-processing does not account for channel
jitter amplification).
To prevent interactions, each element shown in Figure 3 below is joined by
ideal electrical interfaces (outputs have zero impedance and inputs have infinite
impedance).
IBIS-AMI defines several standardized interfaces between the EDA tool and
the algorithmic model for passing impulse response and waveform data. The
initial version 5.0 release of IBIS-AMI had several critical problems and included
unnecessarily complicated modeling scenarios. BIRD 120 addresses these
issues with a refined simulation flow strategy. Only the BIRD 120 flow will be
discussed. Many EDA tool vendors have already implemented the new flow,
including Keysight Technologies with its ADS tool.
As mentioned previously, there are two fundamental simulation flows supported
by IBIS-AMI: a statistical simulation flow for models with LTI equalization
algorithms; and a time-domain flow which permits nonlinear or time-variant
equalization characteristics. In either case, IBIS-AMI simulations begin by
characterizing the channel's impulse response in the time domain. This is typi-
cally accomplished by generating a Heaviside step function at the transmitter's
analog buffer and converting the response at the receiver's analog buffer by
calculating the impulse response using the first-order derivative of the step
response. With the impulse response of the analog channel, noted as hAC(t)
in IBIS-AMI terminology, an IBIS-AMI simulation processes the effects of the
models' filtering functions (equalization) quite differently for time-domain or
statistical methods.
Figure 3. The IBIS-AMI statistical and time-
domain reference flow.
7
For statistical simulation processing, just the block shown in Figure 3 steps
1 to 3 is used. The analog channel impulse response is generated in step 1
and passed to the Tx AMI_Init() and Rx AMI_Init() functions. Typically, the
calls apply signal processing to the impulse response and output the modified
response. These processing functions are noted in Figure 3 as hTEI(t) and hREI(t).
(If the Init_Returns_Impulse setting is false, the call will pass the input response
through without modification). Finally, the EDA tool processes the filtered output
from the Rx AMI_Init() call using its standard statistical simulation process.
The model interaction scenarios for time domain processing are more elaborate
using various combinations of the AMI_Init() and AMI_GetWave() functions.
As discussed earlier, time-domain simulations allow the possibility of modeling
NLTV equalization behaviors. In a time-domain simulation, specific bit stimulus
patterns are applied and the filtered analog (and clock tick) waveforms are
output. The BIRD 120 time-domain reference flow is represented in Figure 3,
steps 1 to 8.
As with the statistical simulation reference flow, the time-domain process
starts by generating the analog channel response which may be combined with
some number of crosstalk aggressors into an impulse matrix and passed to
the Tx AMI_Init() function. Referring to Figure 3, equalization can be applied in
either the AMI_Init() or AMI_GetWave() calls, although applying the filtering in
AMI_GetWave() is obviously preferred since it can support NLTV algorithms.
After the AMI_Init() functions are executed, the stimulus waveform is applied by
the EDA tool in steps 4 and 5 to the Tx AMI_GetWave() function. If the models'
Tx GetWave_Exists is false, the bitstream b(t) is passed through unchanged to
step 6 where it can be convolved with the filtering performed in the AMI_Init()
calls (referred by IBIS-AMI as hTEI(t) or hREI(t) for Tx or Rx respectively). If Tx
GetWave_Exists is true, Tx equalization is applied in the Tx AMI_GetWave()
function (note that hTEI(t) filtering from the Tx AMI_Init() call will not be used so
that the equalization is not double-counted).
If the Rx GetWave_Exists parameter is true, Rx equalization is applied in step
7. The analog waveform is then output to the EDA platform for additional
processing and viewing (this is known as the "Rx Decision Point" in IBIS-AMI
terminology). Also, if the Rx GetWave_Exists parameter is true and the function
supports it, clock ticks from the CDR section of the model can be output to the
tool. For instance, ADS uses the clock tick output to center the eye density and
coutour plots for accurate eye margin measurements. Please note that the flow
shown in Figure 3 is contingent on Tx and Rx Init_Returns_Impulse parameters
being true.
Although the various flow scenarios may appear confusing at first glance,
knowing how a model declares the Init_Returns_Impulse and GetWave_Exists
parameters allows the simulation engineer to quickly understand the type of
simulation to run, how and where filtering is applied, and what to expect for
output.
8
As discussed above, IBIS-AMI provides a standard mechanism to communicate
a model's capability through several IBIS [Reserved_Parameters] in the model
file. They are defined as either true or false:
◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo