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DesignCon 2014




De-Mystifying the 28 Gb/s PCB Channel:
Design to Measurement




Jack Carrel, Xilinx
Heidi Barnes, Agilent Technologies
Robert Sleigh, Agilent Technologies
Hoss Hakimi, Xilinx
Mike Resso, Agilent Technologies
Abstract

A design methodology will be demonstrated for 28 Gb/s SERDES channels using the Xilinx
Virtex-7 Transmitter (Tx) to show the required trade-offs that enable robust performance that is
easy to verify with measurement. Tx and Rx characterization provide information on the
spectral demands for accurate de-embedding of the passive fixture channel; simulation of cables,
connectors, vias, PCB transmission-lines, and package ball-out determine critical elements for
performance; physical routing along with test structures will determine the ability of
measurements to verify performance at the DUT package bumps. Novel 1 port fixture
measurements will be compared with previous full path probing and 2x test fixture measurement
methods to enable reliable fixture removal. Combining design and measurement methodology
enables the capture of 28 Gb/s Tx waveforms at the BGA package bumps even with frequency
dependent losses in the fixture path connection to the measuring oscilloscope.




                                               i
Author(s) Biography

Heidi Barnes, is a Senior Application Engineer for High Speed Digital applications in the EEsof
EDA Group of Agilent Technologies. Past experience includes over 6 years in signal integrity
for ATE test fixtures for Verigy, an Advantest Group, and 6 years in RF/Microwave microcircuit
packaging for Agilent Technologies. She rejoined Agilent Technologies in 2012, and holds a
Bachelor of Science degree in electrical engineering from the California Institute of Technology.

Mike Resso, the Signal Integrity Applications Expert in the Component Test Division of Agilent
Technologies, has over twenty years of experience in the test and measurement industry. His
background includes the design and development of electro-optic test instrumentation for
aerospace and commercial applications. His most recent activity has focused on the complete
multiport characterization of high speed digital interconnects utilizing Time Domain
Reflectometry (TDR) and Vector Network Analysis (VNA). Mike has twice received the Agilent
Technologies Spark of Insight award for his contributions to the company. Mike received a
Bachelor of Science degree in Electrical and Computer Engineering from University of
California.

Rob Sleigh is a Product Marketing Engineer for sampling scopes in Agilent Technologies'
Oscilloscope Products Division. He is responsible for product development for the division's
high-speed electrical and optical digital communications analyzer and jitter test products. Rob's
experience at Agilent Technologies/Hewlett-Packard includes 5 years in technical support, and
over 8 years in sales and technical marketing. Prior to working at Agilent Technologies/HP, Rob
worked for 10 years at Westel Telecommunications in Vancouver, British Columbia, Canada,
designing microwave and optical telecommunication networks. Rob earned his B.S.E.E. degree
from the University of Victoria.

Jack Carrel is an Applications Engineer at Xilinx. He has over 25 years of experience in
product development and design in the fields of Instrumentation, Test and Measurement, and
Telecommunications. His background includes development of electro-optic modules, Multi-
gigabit transceiver boards, high speed and high resolution data acquisition systems for
government and commercial applications. Most recently he has been involved in product design
using multi-gigabit transceivers with specific focus on PCB design issues. He has published in
several professional publications. Jack received his Bachelor of Science degree in Electrical
Engineering from the University of Oklahoma.

Hoss Hakimi is a Principal Engineer at Xilinx. He has 20+ years of experience at various
Telecom, semiconductor, and computer industries specializing on high level behavior modeling
and top-down design methodology in ASIC/FPGA design, synthesis, Substrate Design, 3D
Interconnect Parasitic Extraction, Understanding of high speed signal integrity and PCB power
integrity and simulation. Hoss holds an Electrical Engineering from San Jose State University,
and he has completed MS courses in the EE department at University of California Berkeley.




                                                ii
Introduction
The design of high speed digital systems requires a fundamental understanding of the
degradation encountered in the channel that lies between the transmitter and receiver. Elaborate
coding schemes, equalization, and transmission line structural designs have enabled modern
consumer electronics to easily drive past the RF domain and into the microwave frequencies of
operation. The challenges of a 28 Gb/s channel in support of 100 GB Ethernet are no different
than the original problems of the 1st trans-Atlantic copper communication cable where
transmission line theory dominates and the control of frequency dependent losses along with
reflections are the key to success.

The ability to measure the true 28 Gb/s signal parameters at the device package pins can be quite
challenging. PCB design, fixture path characterization, and instrument measurement capabilities
all contribute to the success of predicting the true signal at the package pins. By systematically
breaking down the data channel, the smaller components within can be optimized and
characterized by both measurement and simulation to achieve a controlled impedance
environment that propagates the highest of data rates Given a clear understanding of the
spectral demands placed on the transmission line by the transmitted data, it is possible to
establish a set of criteria for identifying which transmission line features require attention and
how much effort should be applied.

The design must also accommodate the ability to verify the performance through accurate
measurement techniques. Simple probing with a voltmeter is obviously not an option at 28 Gb/s.
However, well calibrated frequency domain S-parameter type measurements and advanced in-
situ de-embedding techniques have a well-established mathematical solution. These techniques
enable one to "probe" the signal path at arbitrary locations and verify the robust design of the
SERDES channel. The selection of full path probing, vs. a 2x fixture through test structure, vs. a
direct fixture measurement into a reflect open or short is not a simple cost vs. performance trade-
off. The physical design of the channel often dictates the accuracy one can achieve with the
different calibration techniques and there is opportunity to modify the design for improving the
performance of the measurements.

Often the barrier to using advanced error correction techniques such as de-embedding is the cost
in time and materials to develop the necessary calibration structures and the measurement of the
channel fixture. Work in a previously published paper[1] showed that 2x through Automatic
Fixture Removal (AFR) calibration structures can be used to achieve a very acceptable level of
de-embedding quality. As discussed in the previous paper, keys to achieving a useful level of de-
embedding include careful design, construction, and measurement of the calibration test fixture.
It was shown that a calibration test fixture can be designed that does not require an inordinate
amount of board space and does not require the investment in micro-probing stations.
Additionally, if the high speed fixture path is properly designed to avoid large impedance
mismatches, partial S21 de-embedding provided very good results, eliminating the need to
precisely line up measurement reference planes to within picosecond precision for the cascaded
elements in the model of the fixture path. Also, it was shown that high density applications that
have 10's of channels with significant variations in path length (electrical delay) benefitted from
a hybrid measurement based model of the channel fixture so that the effect of path length


                                                 1
variations could be simulated in a matter of seconds and reduce the board space required for 2x
through fixture calibration structures.

Implementation of these measurement calibration techniques can be done with typical stimulus-
response instrumentation such as Vector Network Analyzers or Time Domain Reflectometers.
Knowledge of the spectral demands for the channel will be used to select the required instrument
measurement bandwidth. The measurements will focus on the benefits of a 1 Port calibration
method to provide fast characterization of the channel without the need for test structures or
additional probe connections. In this new 1-Port technique, time domain gating and signal flow
diagram optimization are used to acquire the full 2-port S11, S21, S12, and S22 data set from the
measurement of the fixture channel from the S11 one-port reflection measurement. In this case,
all the S-parameters of the fixture channel are acquired and full de-embedding of the fixture can
be done during in-situ waveform measurements.

The final test of the design and measurement calibration process is to verify that one can get
back to the original performance of a transmitter (Tx) source signal even with the frequency
dependent losses of the fixture channel path in the measurement. The 2x through AFR technique
was verified in a prior publication[1] with the Virtex-7 packaged DUT and can be used as a
reference. This same DUT will be used to evaluate the 1-Port AFR technique and further
evaluate the benefits of a measurement based model. Demonstrating that it is possible to
measure the live signal eye diagram performance at the package bumps of the Xilinx Virtex-7
transmitter opens the door for accurate transmitter models that can be used in the optimization of
application specific channel designs for 28 Gb/s.


Overview of a 28 Gb/s SERDES Channel
A printed circuit board was designed and built with the following goals:
   1. Provide a set of channels for carrying 28 Gb/s signals from the Xilinx FPGA to an
       external device such as a piece of test equipment.
   2. Provide a set of test structures that assist with de-embedding the PCB channel.

The signal path for the 28 Gb/s signals is from the Xilinx Virtex-7 FPGA to SMA connector that
is the working point for connection to devices such as test equipment (e.g. oscilloscopes) or data
transmission devices (e.g. optical transceivers), Figure 1. The components of the signal path are:
     1. BGA to PCB interface structure including the solder ball pad and BGA launch structure
        on the PCB.
     2. Differential loosely coupled embedded stripline traces.
     3. PCB to connector interface structure including vias and connector PCB pads.
     4. Samtec BullsEyeTM connector and test cable.




                                                2
                                                                                                  Samtec

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