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A B C D E
1 1
Compal Confidential
2 2
KBYF0 Schematics Document
AMD Griffin Processor with RS780M+SB700
(With ATI MXM/B)
3
2009-01-22 3
REV:0.3
ZZZ1
PCB
DA60000B600
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/03 Deciphered Date 2009/11/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBYF0 LA-5051P
Date: Tuesday, February 03, 2009 Sheet 1 of 46
A B C D E
A B C D E
Compal Confidential
Model Name : KBYF0 Clock Generator Thermal Sensor
AMD S1G2 Processor Memory BUS(DDRII)
File Name: LA-5051P ICS9LPRS488B ADM1032
page 15 page 5 Dual Channel
1
200pin DDRII-SO-DIMM X2 1
uPGA-638 Package BANK 0, 1, 2, 3 page 8,9
1.8V DDRII 667/800
Fan Control
page 36
page 4,5,6,7
HDMI Conn. LCD Conn. CRT Conn. Hyper Transport Link
page 17 page 16 page 18 16 x 16
ATI RS780M
PCI-Express 16x
MXM III VGA/B
page 14 BGA-528
PCI-Express 1x USB Conn C MOS Bluetooth
2
page 10,11,12,13 Card Reader 5 in 1
2
x4 Camera Conn RTS5159 Socket
port 1,2 port 3
page 29 page 16 page 29 page 25 page 25
MINI Card x2 LAN(GbE) A link
B5 784M Express2 USB port 0,1,2,6 USB port 3 USB port 12 USB port4
TV-Tuner WLAN
page 28 page 26
3.3V 48MHz USB
ATI SB700
3.3V 24MHz HD Audio
RJ45
page 27 S-ATA
BGA-528
SPI
page 19,20,21,22,23
RTC CKT. BIOS ROM MDC 1.5 HDA Codec Int. MIC
page 19
page 21 Conn 32
page
ALC272 33
page page 33
3
BTN/B Conn. LPC BUS SATA HDD Second SATA 3
Digital/Analog MIC.
page 31
Conn.page 24 HDD Conn.24
page
Power On/Off CKT. port 0 port1
page 32 ENE KB926 Audio AMP Mono AMP
LED/B Conn. SATA ODD TPA6017 (for Woofer)
page 31 page 30 page 34 page 34
DC/DC Interface CKT. Conn.page 24
page 37 port 2
Media/B Conn. Touch Pad Int.KBD Phone Jack x2
page 31
page 31 page 31 page 34
FUN/B Conn. CIR EC ROM
page 31 page 32 page 31
4 4
Power Circuit DC/DC USB/B Conn.
page 39,40,41
USB port 0,1,2,6
42,43,44,45 page 28
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/03 Deciphered Date 2009/11/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBKC0 LA-5051P
Date: Tuesday, February 03, 2009 Sheet 2 of 46
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
+CPU_CORE_0 Core voltage for CPU ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE_1 Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_CORE_NB Core voltage for CPU ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.1VS 1.05V switched power rail ON OFF OFF
Board ID / SKU ID Table for AD channel
+1.2V_HT 1.25V switched power rail ON OFF OFF
+NB_CORE 1.0V~1.1V switched power rail for NB VDDC ON OFF OFF
Vcc 3.3V +/- 5%
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
0 0 0 V 0 V 0 V
+2.5VS 2.5V for CPU_VDDA and MXM/B ON OFF OFF
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW 3.3V always on power rail ON ON ON*
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN 3.3V power rail for LAN ON ON ON
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS 3.3V switched power rail ON OFF OFF
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON*
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON*
7 NC 2.500 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 Discrete VGA@
1 0.2 UMA UMA@
No PCI device * 2 0.3 0.4 1.0
3
4
5
6
7
EC SM Bus1 address EC SM Bus2 address PROJECT ID Table
3
Device Address Device Address Board ID PROJECT 3
Smart Battery 0001 011X b ADI ADM1032 1001 100X b 0 KBKC0 (SJM70)
EEPROM(24C16/02) 1010 000X b CPU SB 1001 101X b 1 KBYF0 (SJV70)
MXM GMT G781-1 1001 101X b 2
3
4
SB700 SB700 5
SM Bus 0 address SM Bus 1 address 6
7
Device Address Device Address
Clock Generator 1101 001Xb
(ICS9LPRS365) Lan
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
Minicard
4 Minicard 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/03 Deciphered Date 2009/11/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBYF0 LA-5051P
Date: Tuesday, February 03, 2009 Sheet 3 of 46
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C535 C534 C520 C518 C516 C517
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
<10> H_CADIN[0..15] H_CADON[0..15] <10>
Near CPU Socket
+1.2V_HT +1.2V_HT
JCPU1A
2 2
VLDT=500mA D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2
D2 AE3 C533 4.7U_0805_10V4Z
VLDT_A1 VLDT_B1
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
H_CLKIP0 J3 Y1 H_CLKOP0
<10> H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 <10>
H_CLKIN0 J2 W1 H_CLKON0
<10> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 <10>
H_CLKIP1 J5 Y4 H_CLKOP1
<10> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <10>
H_CLKIN1 K5 Y3 H_CLKON1
<10> H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 <10>
H_CTLIP0 N1 R2 H_CTLOP0
<10> H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 <10>
H_CTLIN0 P1 R3 H_CTLON0
<10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10>
H_CTLIP1 P3 T5 H_CTLOP1
<10> H_CTLIP1 L0_CTLIN_H1 L0_CTLOUT_H1 H_CTLOP1 <10>
H_CTLIN1 P4 R5 H_CTLON1
<10> H_CTLIN1 L0_CTLIN_L1 L0_CTLOUT_L1 H_CTLON1 <10>
6090022100G_B
Athlon 64 S1
Processor Socket
CONN@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/03 Deciphered Date 2009/11/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KBYF0 LA-5051P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 03, 2009 Sheet 4 of 46
A B C D E
A B C D E
Processor DDR2 Memory Interface
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH JCPU1C
<9> DDRB_SDQ[63..0]
MEM:DATA DDRA_SDQ[63..0] <8>
DDRA_CLK0 DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.8V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDRB_SDQ2 A14 H14 DDRA_SDQ2
C244 DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2
1.5P_0402_50V9C DDRB_SDQ4 G11 H11 DDRA_SDQ4
R79 DDRA_CLK0# 2 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDRB_SDQ6 D12 C13 DDRA_SDQ6
DDRA_CLK1 DDRB_SDQ7 MB_DATA6 MA_DATA6 DDRA_SDQ7
A13 MB_DATA7 MA_DATA7 E13
1 DDRB_SDQ8 A15 H15 DDRA_SDQ8
1
+MCH_REF DDRB_SDQ9 MB_DATA8 MA_DATA8 DDRA_SDQ9
A16 MB_DATA9 MA_DATA9 E15
1000P_0402_50V7K
0.1U_0402_16V4Z
C178 DDRB_SDQ10 A19 E17 DDRA_SDQ10
MB_DATA10 MA_DATA10
2
1 1 1.5P_0402_50V9C DDRB_SDQ11 A20 H17 DDRA_SDQ11
2 MB_DATA11 MA_DATA11
C181
C189
R78 DDRA_CLK1# DDRB_SDQ12 C14 E14 DDRA_SDQ12
1K_0402_1% DDRB_SDQ13 MB_DATA12 MA_DATA12 DDRA_SDQ13
D14 MB_DATA13 MA_DATA13 F14
DDRB_SDQ14 C18 C17 DDRA_SDQ14
2 2 DDRB_CLK0 DDRB_SDQ15 MB_DATA14 MA_DATA14 DDRA_SDQ15
D18 G17
1
DDRB_SDQ16 MB_DATA15 MA_DATA15 DDRA_SDQ16
1 D20 MB_DATA16 MA_DATA16 G18
DDRB_SDQ17 A21 C19 DDRA_SDQ17
C509 DDRB_SDQ18 MB_DATA17 MA_DATA17 DDRA_SDQ18
D24 MB_DATA18 MA_DATA18 D22
1.5P_0402_50V9C DDRB_SDQ19 C25 E20 DDRA_SDQ19
DDRB_CLK0# 2 DDRB_SDQ20 MB_DATA19 MA_DATA19 DDRA_SDQ20
B20 MB_DATA20 MA_DATA20 E18
DDRB_SDQ21 C20 F18 DDRA_SDQ21
DDRB_CLK1 DDRB_SDQ22 MB_DATA21 MA_DATA21 DDRA_SDQ22
B24 MB_DATA22 MA_DATA22 B22
1 DDRB_SDQ23 C24 C23 DDRA_SDQ23
DDRB_SDQ24 MB_DATA23 MA_DATA23 DDRA_SDQ24
E23 MB_DATA24 MA_DATA24 F20
C447 DDRB_SDQ25 E24 F22 DDRA_SDQ25
1.5P_0402_50V9C DDRB_SDQ26 MB_DATA25 MA_DATA25 DDRA_SDQ26
G25 MB_DATA26 MA_DATA26 H24
DDRB_CLK1# 2 DDRB_SDQ27 DDRA_SDQ27
G26 MB_DATA27 MA_DATA27 J19
DDRB_SDQ28 C26 E21 DDRA_SDQ28
DDRB_SDQ29 MB_DATA28 MA_DATA28 DDRA_SDQ29
D26 MB_DATA29 MA_DATA29 E22
DDRB_SDQ30 G23 H20 DDRA_SDQ30
+0.9V +0.9V DDRB_SDQ31 MB_DATA30 MA_DATA30 DDRA_SDQ31
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