Service Manuals, User Guides, Schematic Diagrams or docs for : Compal Compal_LA-2361
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5 4 3 2 1
Project Code : AL50/1
D
Date : 2004-06-02 D
Revision : 0.2
C C
AL50/1 Intel Sonoma plateform Used the Alvisio and ICH6-M
B B
A A
Compal Electronics, Inc.
Title
Function
Size Document Number Rev
LA-2361 0.0
Date: Monday, October 04, 2004 Sheet 1 of 50
5 4 3 2 1
5 4 3 2 1
Compal confidential Block Diagram
Dothan
D Clock Generator D
uFCPGA CPU ICS
Memory
HA#(3..31) HD#(0..63) BUS(DDR) Fan Control X1
System Bus
400 / 533MHz Dual Channel
CRT CONN. 2.5V 333MHz SO-DIMM X 1
BANK 0, 1
VGA & TV-OUT Alviso Intel 915 PM/GM SO-DIMM X 1 LED/B
BANK 2, 3
Board GMCH-M Channel A
Internal GM
ATI VGA 1257 FC-BGA SW LED BD
VGA CONN. PCI-E 16X
C
External PM C
T/P
DMI
1.5V
MINI PCI 100MHz BT+MDC DC IN
3.3V 24.576MHz AC-LINK BATT IN/+2.5V
3.3V 33MHz PCI BUS 3.3V 33MHz
IDSEL:AD17
ICH6
(PIRQA/B#,GNT#2,REQ#2)
609 BGA
RTL 8110SBL AC97 CODEC 1.5V/1.05V(+VCCP)
VIA6301 CardBus / G 8100CL / ATA100 RTL 250
1394 Controller 100
B ENE CB712 B
5V/3.3V/15V
HDD CDROM
Transformer
1394 SDIO Slot 0 & RJ45 AMP &
CONN. CONN. LPC BUS
3.3V 33MHz Phone/ MIC
Jack 1.8V / 0.9V
USBPORT 0
JUSBP2
USBPORT 1
JUSBP3 VCORE
X BUS 48MHz / 480Mb USBPORT 2
USB2.0 BT
SIO USBPORT 3
KB910 JUSBP1
LPC47N217D USBPORT 4 CHARGER
SST39VF080 JUSBP1
USBPORT 5
A RESERVED A
USBPORT 6
FIR PIO Touch Pad Int.KBD RESERVED
USBPORT 7
RESERVED
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Block Diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-2361 0.0
Date: Monday, October 04, 2004 Sheet 2 of 50
5 4 3 2 1
5 4 3 2 1
I2C / SMBUS ADDRESSING Power Managment table
PCB Rev Data
External PCI Devices
Signal Bringup-Build 0.1
+CPU_CORE SST-Build
+VCCP
D
DEVICE IDSEL # REQ/GNT # PIRQ +5VS PT-Build D
LAN AD17 0 F +3VS
State +2.5V +2.5VS
CARD BUS AD20 1 A +12VALW +3V +1.8VS
+3VALW +5V +1.25VS ST-Build
Cardreader B +5VALW +12V +1.5VS
1394 AD16 2 E
S0 ON ON ON QT-Build
Wireless LAN(MINI PCI) AD18 3 G,H
S1 ON ON ON
S3 ON ON OFF
S5 S4/AC ON OFF OFF
@ Depop SCHEMATICS VERSION LIST
S5 S4/AC don't exist OFF OFF OFF
1@ EAL51 VERSION ISSUE DATE REMARK
C 2@ EAL50 C
0.0A First Release
1@ EAL51 VALUE (DELETE SIO/1394) Ceramic Capacitor Spec
Guide:
Temperature Characteristics:
Symbol 0 1 2 3 4 5 6 7
CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R
8 9 A B C D E F G
NP0 C0G BJ CH CJ CK SH SJ
H I J
UJ UK SL
B
Tolerance: B
Symbol A B C D F G H J
CODE +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1PF +-2% +-3% +-5%
K M N P Q V X Z
+-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20%
SMBUS Control Table
THERMAL THERMAL VGA Thermal
SOURCE INVERTER BATT SERIAL SENSOR SENSOR SODIMM CLK CHIP MINI PCI LCD
EEPROM (CPU) (LM75) ADM1032
SMB_EC_CK1 PC87591L
SMB_EC_DA1
SMB_EC_CK2 PC87591L
A SMB_EC_DA2 A
ICH_SMBCLK
ICH6-M
ICH_SMBDATA
LCD_DDCCLK Alviso Title
LCD_DDCDATA GM-GP
Size Document Number Rev
Custom LA-2361 0.0
Date: Monday, October 04, 2004 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1
+5VALW
D PWR_SRC D
ADAPTER
+3VALW
BATTERY
SUSPWROK_1.5V
SUSPWROK_5V
SUSPWROK_5V
C C
RUNPWROK
RUNPWROK
SUS_ON
SUS_ON
+5V +3VSRC +VCC_CORE +1.5V +VCCP +1.8VSUSP +2.5V_DDR_VTT
AUDIO_AVDD_ON
SUSPWROK_5V
PJP11,PJP12
RUN_ON_D
(Option)
RUN_ON
B B
RUN_ON
PL9
+15V VDDA +3VS V3P3LAN +3V +2.5VS +1.5VS +1.8V
RUN_ON
L10
RUN_ON
A
+1.8VS A
+5VHDD +5VMOD +5VS
Title
<Title>
Size Document Number Rev
Custom LA-2361 0.0
Date: Monday, October 04, 2004 Sheet 4 of 50
5 4 3 2 1
5 4 3 2 1
+3V
<8> H_A#[3..31] H_D#[0..63] <8>
JCPU1A R79
150_0402_5%
Dothan
H_A#3 P4 A19 H_D#0 1 2 ITP_DBRESET#
H_A#4 A3# D0# H_D#1
U4 A4# D1# A25
H_A#5 V3 A22 H_D#2
H_A#6 A5# D2# H_D#3
H_A#7
R3
V2
A6# D3# B21
A24 H_D#4
Test pad as closed as posible +VCCP
H_A#8 A7# D4# H_D#5 R90
W1 B26
H_A#9 A8# D5# H_D#6 54.9_0603_1%
T4 A21
D H_A#10 A9# D6# H_D#7 ITP_DBRESET# PAD T7 ITP_TDO D
W2 B20 1 2
H_A#11 A10# D7# H_D#8 R76
Y4 C20
H_A#12 A11# D8# H_D#9 ITP_BPM#0 PAD T6 54.9_0603_1%
Y1 B24
H_A#13 A12# D9# H_D#10 H_RESET#
U1 D24 1 2
H_A#14 A13# D10# H_D#11 ITP_BPM#1 PAD T8
AA3 E24
H_A#15 A14# D11# H_D#12 ITP_BPM#5
Y3 C26 1 2
H_A#16 A15# D12# H_D#13 ITP_BPM#2 PAD T10 R745 56_0402_5%
AA2 B23
H_A#17 A16# D13# H_D#14
AF4 E23
H_A#18 A17# D14# H_D#15 Place near JITP 0.5" ITP_BPM#3 PAD T9
AC4 C25
H_A#19 A18# D15# H_D#16
AC7 H23
H_A#20 A19# D16# H_D#17 ITP_BPM#4 PAD T12 +VCCP R479 39.4
AC3 G25
H_A#21 A20# D17# H_D#18 R74 37.4_0402_1%
AD3 A21# D18# L23
H_A#22 AE4 M26 H_D#19 22.6_0402_1% ITP_BPM#5 PAD T11 1 2 ITP_TMS
H_A#23 A22# D19# H_D#20 H_RESET# PAD T4 R85
AD2 A23# D20# H24 1 2
H_A#24 AB4 F25 H_D#21 ITP_TCK PAD T17 150_0402_5%
H_A#25 A24# D21# H_D#22 ITP_TDI
AC6 A25# ADDR GROUP DATA GROUP D22# G24 1 2
H_A#26 AD5 J23 H_D#23 R87 CLK_ITP_R# PAD T18 This shall place near CPU
H_A#27 A26# D23# H_D#24 22.6_0402_1% CLK_ITP_R PAD T19 R100
AE2 A27# D24# M23
H_A#28 AD6 J25 H_D#25 ITP_TDO 1 2 PAD T15 680_0402_5%
H_A#29 A28# D25# H_D#26 ITP_TRST#
AF3 A29# D26# L26 1 2
H_A#30 AE1 N24 H_D#27 R106
H_A#31 A30# D27# H_D#28 27.4_0402_1%
<8> H_REQ#[0..4] AF1 A31# D28# M25
H26 H_D#29 ITP_TRST# PAD T16 1 2 ITP_TCK
H_REQ#0 D29# H_D#30 ITP_TMS PAD T13
R2 REQ0# D30# N25
H_REQ#1 P3 K25 H_D#31 ITP_TDI PAD T14
H_REQ#2 REQ1# D31# H_D#32
T2 REQ2# D32# Y26
H_REQ#3 P1 AA24 H_D#33
REQ3# D33#
CLK_ITP_R# 1
R110 2 0_0402_5%
H_REQ#4 T1 REQ4# D34# T25
U23
H_D#34
H_D#35 Check ITP connector.
CLK_ITP_R 1
R112 H_ADSTB#0 D35# H_D#36
2 0_0402_5% <8> H_ADSTB#0 U3 ADSTB0# D36# V23
@ H_ADSTB#1 AE5 R24 H_D#37
<8> H_ADSTB#1 ADSTB1# D37# H_D#38 +VCCP
@ D38# R26
C H_D#39 C
D39# R23
CLK_ITP @ R111
1 2 0_0402_5% CPU_CK_ITP A16 AA23 H_D#40 1
<18> CLK_ITP CLK_ITP# ITP_CLK0 D40#
<18> CLK_ITP#
@ R109
1 2 0_0402_5% CPU_CK_ITP# A15 ITP_CLK1 D41# U26 H_D#41 C359
V24 H_D#42
CLK_CPU_BCLK D42# H_D#43 0.1U_0402_10V6K
<18> CLK_CPU_BCLK B15 BCLK0 D43# U25
CLK_CPU_BCLK# B14 HOST CLK V26 H_D#44 2
<18> CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46
AA26
D46# H_D#47
Y25
H_ADS# D47# H_D#48
<8> H_ADS# H_BNR#
N2
ADS# D48#
AB25
H_D#49
Place near JITP
<8> H_BNR# L1 AC23
H_BPRI# BNR# D49# H_D#50
<8> H_BPRI# J3 AB24
H_BR0# BPRI# D50# H_D#51
<8> H_BR0# N4 AC20
H_DEFER# BR0# D51# H_D#52
<8> H_DEFER# L4 AC22
H_DRDY# DEFER# D52# H_D#53 +3VS
<8> H_DRDY# H2 AC25
H_HIT# DRDY# D53# H_D#54
<8> H_HIT# K3 AD23
H_HITM# HIT# D54# H_D#55
56_0402_5% R78
<8> H_HITM# K4
HITM# CONTROL GROUP D55#
AE22
+VCCP
1 2 H_IERR# A4 AF23 H_D#56
+VCCP IERR# D56#
1
H_LOCK# J2 AD24 H_D#57
<8> H_LOCK# H_RESET# LOCK# D57# H_D#58
B11 AF20 R132
<8> H_RESET# RESET# D58# H_D#59
AE21 1K_0402_5%
D59# H_D#60
<8> H_RS#[0..2] AD21
H_RS#0 D60# H_D#61
H1 AF25
2
RS0# D61#
1
H_RS#1 K1 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63 R124
L2 AF26
H_TRDY# RS2# D63#
<8> H_TRDY# M3 56_0402_5%
TRDY#
PROCHOT# <32,34>
D25
2
DINV0# H_DINV#0 <8>
1
1
J26 R123 C
ITP_BPM#0 DINV1# H_DINV#1 <8>
C8 T24 56_0402_5% 2 Q6
ITP_BPM#1 BPM0# DINV2# H_DINV#2 <8> B
B8 AD20 2SC2411K_SC59
ITP_BPM#2 BPM1# DINV3# H_DINV#3 <8> E
A9
3
B ITP_BPM#3 BPM2# B
C9
2
BPM3# H_DSTBN#[0..3] <8>
C23 H_DSTBN#0
ITP_DBRESET# DSTBN0# H_DSTBN#1 H_PROCHOT#
A7 K24
H_DBSY# DBR# DSTBN1# H_DSTBN#2
<8> H_DBSY# M2 W25
H_DPSLP# DBSY# DSTBN2# H_DSTBN#3
<20> H_DPSLP# B7 AE24 H_DSTBP#[0..3] <8>
H_DPRSLP# DPSLP# DSTBN3# H_DSTBP#0
<20> H_DPRSLP# G1 C22
DPRSTP# DSTBP0# H_DSTBP#1
<8> H_DPWR# C19 L24
ITP_BPM#4 DPWR# DSTBP1# H_DSTBP#2
A10
PRDY# MISC DSTBP2#
W24
ITP_BPM#5 B10 AE25 H_DSTBP#3
H_PROCHOT# PREQ# DSTBP3#
</pre><br><br>
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