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A B C D E
1 1
2
Compal confidential 2
Schematics Document
Mobile C-7M uFBGA with
3
VIA 896 NB & 8237S SB 3
2008-04-03
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/03 Deciphered Date 2009/04/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3941P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 03, 2008 Sheet 1 of 40
A B C D E
A B C D E
Compal confidential
File Name : LA-3941P
Thermal Sensor VIA C7M 1G Clock Generator
1 ICS9LPR704AGLF 1
ADM1032AR uFBGA CPU
page 11
page 5 400 pins
page 4,5
FSB
CRT CONN
single channel
North Bridge
page 12
DDR2-SO-DIMM X1
DDRII 667MHz 1.8V BANK 0, 1, 2, 3
LCD CONN LVDS VT 1637 VN 896
page 10
page 13 page 13
Dual Channel
951 pins
PCI-E BUS page 6,7,8,9
2 2
Power USB conn
V-Link page 25
USB2.0
10/100/1000 LAN Mini-Card USB conn x 2
South Bridge
page 25
BCM5784/BCM5787 WLAN
page 18
Azalia
PCI BUS VT 8237S RJ11 CONN
page 19
IDE MDC V1.5
542 pins page 28 page 28
SATA
page 15,16,17
RJ45 CONN Audio CKT TPA6041
page 20 CardBus Controller AMP & Audio Jack
AD1984AHD page 23
page 24
Ricoh R5C847
page 21
SPI ROM SSD_FM1024A10C5G
page 28
page 18
3 3
CardBus SD/MMC ODD CONN
page 22 page 22
page 18
LPC BUS
1.8" SATA CONN
page 18
LED TPM1.2 SMSC 1070
page 28 SLB9635TT Docking CONN.
page 25 page 27
*RJ-45(LED*2)
*CRT
RTC CKT. *LINE IN
page 15 Touch Pad Int.KBD *LINE OUT
page 28 page 28 *USB x2
*DC JACK
4
Power On/Off CKT. TrackPoint 4
page 28 page 26
page 28
Security Classification Compal Secret Data Compal Electronics, Inc.
DC/DC Interface CKT. Issued Date 2008/04/03 Deciphered Date 2009/04/03 Title
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 29 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3941P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 03, 2008 Sheet 2 of 40
A B C D E
A
Voltage Rails
+B +5VALW +1.8V +5VS
LDO3 +3VALW +3VS
power
Install below 43 level BOM structure for ver. 0.6
plane LDO5 +1.5VALW +1.8VS
+1.5VS
+1.6VS_NB
+CPU_CORE DEBUG@ : means just build when PCIE port 80 CARD function enable. Remove before MP
+VCCP NO1394@ : means just build without 1394 function
+0.9VS
State 5787@ : means just build when 5787 function enable.
+VCCA
SSC@ : means just build when LVDS SS function enable.
S0 O O O O
Install below 45 level BOM structure for ver. 0.6
S1
O O O O 45@ : means just put it in the BOM 0f 45 level.
S3
O O O X
S5 S4/AC
O O X X Reserve below BOM structure for ver. 0.6
@ : means just reserve , no build
S5 S4/ Battery only
O X X X CONN@ : means ME part.
S5 S4/AC & Battery BT@ : means just build when BT function enable. Install at DB-1 only
don't exist X X X X
NOSSC@ : means just build when LVDS SS function disable.
O MEANS ON X MEANS OFF 5784@ : means just build when 5784 function enable.
PCI Devices TPM@ : means just build when TPM function enable. Install at DB-2, SI-1 only
1394@ : means just build when 1394 function enable. Remove before MP
1 1
HDD@ : means just build when 1.8" SATA HDD function enable. Remove before MP
SMBUS Control Table
THERMAL CAP
SOURCE BATT SENSOR SODIMM CLK CHIP MINI CARD LCD SENSOR
(CPU)
SMB_EC_CK1
SMB_EC_DA1
EC
V X X X X X X
Cap_CLK
Cap_DAT
EC X X X X X X V
SB_SMCLK
SB_SMDATA SB X V V V V X X
LCD_CLK
LCD_DAT NB X X X X X V X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/03 Deciphered Date 2009/04/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3941P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 03, 2008 Sheet 3 of 40
A
5 4 3 2 1
U1A
6 HA[3:31]
HA3 F3 A3# A20M# B9 H_A20M# 15 06/11
HA4 H3 A8 FERR_CPU#
HA5 A4# FERR# +3VL H_PWRGD
J1 A5# INIT# A10 H_INIT# 15
HA6 F2 B8 +VCCP
A6# INTR H_INTR 15
HA7 J2 C9 U38C
14
A7# NMI H_NMI 15
HA8 K1 D9 BREQ1# R1 1 2 100_0402_5%
A8# IGNNE# H_IGNNE# 15 D
1
HA9 G3 C10 BREQ2# R2 1 2 100_0402_5%
H_SMI# 15
P
HA10
A9# SMI# Q60 BREQ3# R3 100_0402_5%
K3 A10# SLP# A11 H_CPUSLP# 6,15 15,21,27 SB_PWRGD 5 I O 6 2 1 2
HA11 L2 B10 G 2N7002_SOT23 H_PSI# R4 1 2 51.1_0402_1%
A11# STPCLK# H_STPCLK# 15
G
D HA12 L3 A18 S D
A12# DPWR# DPWR# 6
3
HA13 J3 B1
A13# ADS# ADS# 6
7
HA14 M3 D3
A14# BNR# BNR# 6
HA15 L1 A1
A15# DBSY# DBSY# 6
HA16 M1 A2
A16# DEFER# DEFER# 6
N2 A4 TC74LCX14FT_TSSOP14
A17# DRDY# DRDY# 6
N3 A18# HIT# B3 HIT# 6
HA30 N1 C3
A30# HITM# HITM# 6
TRDY# B2 HTRDY# 6
BPRI# C4 BPRI# 6
C1 BREQ0#
BREQ0# BREQ0# 6
U1 BREQ1#
BREQ1# BREQ2# +VCCP
BREQ2# C5
21X21 D5 BREQ3#
BREQ3#
LOCK# D4 HLOCK# 6
H_STPCLK# R7 1 2 150_0402_5%
H_INTR R8 150_0402_5%
NANO BGA REQ0# D1 HREQ0# 6 1 2
D2 H_IGNNE# R9 1 2 150_0402_5%
REQ1# HREQ1# 6
F1 H_A20M# R10 1 2 150_0402_5%
REQ2# HREQ2# 6
H_SMI# R12 1 2 150_0402_5%
H_CPUSLP# R13 1 2 150_0402_5%
HD0 A20 B4 H_INIT# R14 1 2 150_0402_5%
6 HD[0:63] D0# RS0# RS0# 6
HD1 F18 A3 06/06 VIA H_NMI R15 1 2 150_0402_5%
D1# RS1# RS1# 6
HD2 D18 E3 PROCHOT# R16 1 2 150_0402_5%
D2# RS2# RS2# 6
HD3 C19 H_DPSLP# R17 1 2 150_0402_5%
D3# CPU_BSEL0 R18
HD4 E18 D4# ASTBN0# G1 HA_STB0N# 6 1 2 150_0402_5%
@
HD5 H20 G2 CPU_BSEL1 R20 1 @
2 150_0402_5%
D5# ASTBP0# HA_STB0P# 6
C HD6 C20 C
HD7 D6#
C18 D7#
HD8 B19 E19
D8# DSTBP0# HD_STBP0# 6
HD9 E20 F19 +VCCP
D9# DSTBN0# HD_STBN0# 6
HD10 G20 U20
D10# DSTBP1# HD_STBP1# 6
HD11 G18 T20
D11# DSTBN1# HD_STBN1# 6
HD12 J18 W15 FERR_CPU# 1 2
D12# DSTBP2# HD_STBP2# 6
HD13 D20 V15 R21
D13# DSTBN2# HD_STBN2# 6
HD14 F20 Y6 51.1_0402_1%
D14# DSTBP3# HD_STBP3# 6
HD15 H18 D15# DSTBN3# Y5 HD_STBN3# 6 06/23 BIOS
HD16 L19 TRIP_CPU# 1 2
HD17 D16# R23
L18 D17# BCLK A14 CLK_BCLK 11
HD18 U19 A13 51.1_0402_1%
D18# BCLK# CLK_BCLK# 11
HD19 V19 PROCHOT# 3 1 H_PROCHOT#
D19# H_PROCHOT# 16
HD20 M20 C14 CPU_BSEL0 Q1
HD21
D20# BSEL0 CPU_BSEL1 @ MMBT3904_SOT23
K19 D21# BSEL1 D14
HD22 K20 D22#
2
HD23 N20 C13 1 2
D23# RESET# H_RST# 6 +VCCP
HD24 R19 C8 H_PWRGD R24 @ 10K_0402_5%
HD25 D24# PWRGD +VCCP
P19 D25#
HD26 P18 D26# BREQ0# R25
HD27 U18 D27# 1 2 200_0402_5%
HD28 W20 H_PWRGD R26 1 2 51.1_0402_1%
D28# H_RST# R27
HD29 M19 D29# PSI# C7 H_PSI# 35 1 2 51.1_0402_1%
@
HD30 T18
HD31 D30# CPU_COMP0 The resistors need to place within
R20 D31# COMP0 H17
HD32 Y12 200mil of the processor. TRIP_CPU# 3 1
D32# H_THERMTRIP# 16
HD33 V13 T3 CPU_COMP2 Q2
HD34 D33# COMP2 MMBT3904_NL_NPN_SOT23
B Y17 D34# MPI U5 B
HD35 W17 D35#
2
HD36 V16 C17
D36# THERMDA H_THERMDA 5
HD37 Y19 A17 1 2
D37# THERMDC H_THERMDC 5 +VCCP
HD38 W18 A16 TRIP_CPU# R29 10K_0402_5%
HD39
D38# THERMTRIP# PROCHOT#
V18 D39# PROCHOT# B18
HD40 W12 CPU_COMP2 R34 1 2 27.4_0402_1%
HD41
D40# DPB0 T1 PAD +3VS TCK R35 47_0402_5%
Y14 D41# DP0# J20 1 2
HD42 Y13 R18 DPB1 T2 PAD TRST# R36 1 2 680_0402_5%
HD43
D42# DP1# DPB2 T3 PAD R39 CPU_COMP0 R37 27.4_0402_1%
Y16 D43# DP2# V11 1 2
1
HD44 W14 Y10 DPB3 T4 PAD
HD45 D44# DP3# 10K_0402_5%
Y11 D45#
HD46 V12 B11
D46# DPSLP# H_DPSLP# 15
HD47 V14
HD48
D47# TDI FERR_CPU#
W10 D48# TDI C15 3 1 FERR# 15
2
HD49 Y8 A15 TDO Q3
HD50 D49# TDO TMS MMBT3904_NL_NPN_SOT23 +VCCP
V10 D50# TMS B15
HD51 W4 B16 TRST#
D51# TRST#
2
HD52 W7 C16 TCK +VCCP
HD53
D52# TCK
Y9 D53# 1 2
HD54 W8 B7 R42 10K_0402_5%
D54# VID0 CPU_VID0 35
HD55 W5 C6 TDI R40 1 2 150_0402_5%
D55# VID1 CPU_VID1 35
HD56 V6 A7 TDO R41 1 2 150_0402_5%
D56# VID2 CPU_VID2 35
HD57 V9 B6 TMS R43 1 2 47_0402_5%
D57# VID3 CPU_VID3 35
HD58 V3 A6 H_DPSLP# 1 2
D58# VID4 CPU_VID4 35
HD59 Y3 A5 C756 0.1U_0402_16V4Z
D59# VID5 CPU_VID5 35
HD60 Y4 H_CPUSLP# 1 2
HD61 D60# DBI3# C757 0.1U_0402_16V4Z
V7 D61# DINV3# V5 DBI3# 6
HD62 V4 V17 DBI2# H_PWRGD 1 2
A D62# DINV2# DBI2# 6 A
HD63 V8 N18 DBI1# C758 0.1U_0402_16V4Z
D63# DINV1# DBI1# 6
H19 DBI0#
DINV0# DBI0# 6
ZZZ1 C7-M ULV 3.5W 1G/400_NANOBGA2-400 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/03 Deciphered Date 2009/04/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU PART1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PCB 03B LA-3941P REV1 M/B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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