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A B C D E
Model Name: KML50 DIS
PCB NO: LA-4595PR04
BOM P/N: DA80000DR00
1 1
Half Penny Bridge 15.4
2 Compal Confidential 2
Schematic Document
Cantiga + ICH9
2009 / 02 / 17 Rev:1.0(A00)
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4595P
Date: Tuesday, February 17, 2009 Sheet 1 of 49
A B C D E
A B C D E
Compal confidential
File Name : LA-4595P
Half Penny Bridge 15.4 DIS
ZZZ1
1
PCB Thermal Sensor Penryn -4MB (Socket P) 1
+CPU_CORE
EMC1402-2-ACZL-TR
CRT +VCCP
uFCPGA-478 CPU
+CRT_VCC P.16
+3VS P.4
P.4,5,6
+1.5VS CK505 TSSOP-64
LVDS Panel Interface Fan conn Clock Generator
+5VS P.4 H_A#(3..35)
+B+ FSB ICS9LPRS387AKLFT
+3VS P.16 H_D#(0..63) 800/1066MHz 1.05V
+LCDVDD +1.05VS_CK505
DDR2 667/800MHz 1.8V DDR2-SO-DIMM X2 +3VS_CK505 P.15
BANK 0, 1, 2, 3
Intel Cantiga MCH +1.8V +0.9VS
P.13,14
nVidia 1329pin BGA
NB9M-GS +VCCP Dual Channel
+3VS_DAC_CRT
+VGA_CORE +1.05VS_DPLLA
+3VS_DAC_BG
VRAM x 2 +1.1V_GFX_PCIE +1.05VS_DPLLB USB conn x 4
+1.8VS P.35 +1.8VS +1.8V_TXLVDS P.7,8,9,10,11,12 +USB_AS +USB_BS +USB_CS P.29
2
+3VS P.31,32,33,34 2
CardBus Controller DMI X4 C-Link FingerPrinter
+3VS P.29
PCI -E BUS
O2MICRO OZ888
+1.8VS_CB
Felica Conn
+3VS_PHY P.30 USB2.0 +5VS P.29
Intel ICH9-M Azalia
BT Conn
1394 Media Card
+3VS_CR
+RTCVCC
+3VS P.29
+1.5VS
PCI-E BUS 676pin BGA SATA 0
+VCCP SATA 1
+3VALW P.17,18,19,20 Camera
+3VS +5VS P.16
10/100/1000 LAN Mini-Card-2 Mini-Card-1 Express Card Express Card
REALTEK (WLAN)
+1.5VS
(WWAN)
+1.5VS
+1.5VS +3VS +1.5VS P.26
+3VS P.23 P.23 +3VS P.26
RTL8111DL P.21
+LAN_IO
+3VS
3 3
Mini-Card-1 P.23
+3VS +1.5VS
RJ45/11 CONN SIM CON
P.21 +UIM_PWR
LPC BUS Mini-Card-2 P.23
+3VS +1.5VS
Digi Mic
+3VS P.16
TPM Audio CODEC
SLB 9635 IDT92HD81 P.24 Audio Jack
Mini-Card-2 P.23 +3VALW
ENE KB926 +3VALW
+5VS +3VS
+3VS +1.5VS +MIC1_VREFO P.24
+EC_AVCC P.27 +3VS P.28
SATA HDD Connector
+5VS P.22
Touch Pad CONN. Int.KBD BIOS(System/EC)
Power On/Off CKT. +5VS +3VALW
P.28 P.28 P.27
+3VALW P.28 CDROM Conn.
4
+5VS P.22 4
DC/DC Interface CKT. RTC CKT.
+3VS +5VS P.36 +RTCVCC P.18
Security Classification Compal Secret Data Compal Electronics, Inc.
2007/1/15 2008/1/15 Title
Power Circuit DC/DC Issued Date Deciphered Date
Block diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P.39~P.49 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4595P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 17, 2009 Sheet 2 of 49
A B C D E
A
Symbol Note :
O MEANS ON X MEANS OFF
Voltage Rails
: means Digital Ground
+5VS
+3VS
+1.5VS : means Analog Ground
power
plane +0.9VS
+VCCP @ : means just reserve , no build
+5VALW +1.8V +CPU_CORE CON@ : means ME connectors
+B +VGA_CORE TPM@ : means TPM function
+3VALW +1.8VS
+1.1V_GFX_PCIEP
State
PCI EXPRESS DESTINATION SATA DESTINATION
Lane 1 MINI CARD-1 WWAN Lane 0 HDD
Lane 2 GLAN RTL8111DL Lane 1 ODD
S0
O O O O Lane 3 MINI CARD-2 WLAN Lane 4 NA
S1
O O O O Lane 4 EXPRESS CARD Lane 5 NA
S3
O O O X Lane 5 CARD READER OZ888
S5 S4/AC
O O X X Lane 6 NA
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X
SMBUS Control Table
USB PORT# DESTINATION
1 1
THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD
0 JUSBP1
1 CAMERA SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
2 JUSBP3 TOP SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
SMB_CK_CLK1
3 Felica SMB_CK_DAT1 ICH9 X X X X V V X X
4 Blue Tooth LCD_CLK
ICH9-M LCD_DAT Cantiga
X X X X X X X V
5 Finger Printer
6 JMINI2-WLAN
I2C / SMBUS ADDRESSING
7 Express card
DEVICE HEX ADDRESS
8 JUSBP3 BOT DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
9 JMINI1-WWAN CLOCK GENERATOR (EXT.) D2 11010010
LED panel 58 01011000
10 JUSBP4
11 NA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4595P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 17, 2009 Sheet 3 of 49
A
5 4 3 2 1
+VCCP
XDP_TDI R5 1 2 54.9_0402_1%
XDP_TMS R4 1 2 54.9_0402_1%
D D
XDP_TRST# R11 1 2 54.9_0402_1%
XDP_TCK R35 1 2 54.9_0402_1%
<7> H_A#[3..16]
CONN@ This shall place near CPU
JCPU1A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# <7>
ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
H_A#5 A[4]# BNR# H_BPRI# H_BNR# <7>
L4 A[5]# BPRI# G5 H_BPRI# <7>
H_A#6 K5
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21 H_DRDY#
H_A#9 A[8]# DRDY# H_DBSY# H_DRDY# <7>
J1 A[9]# DBSY# E1 H_DBSY# <7>
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <7>
H_A#12 P2 A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# <18>
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# <7>
H_ADSTB#0 M1
<7> H_ADSTB#0 ADSTB[0]# H_RESET#
RESET# C1 H_RESET# <7>
H_REQ#0 K3 F3 H_RS#0
<7> H_REQ#0 H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_RS#0 <7>
<7> H_REQ#1 H2 REQ[1]# RS[1]# F4 H_RS#1 <7>
H_REQ#2 K2 G3 H_RS#2
<7> H_REQ#2 H_REQ#3 REQ[2]# RS[2]# H_TRDY# H_RS#2 <7>
<7> H_REQ#3 J3 REQ[3]# TRDY# G2 H_TRDY# <7>
H_REQ#4 L1
<7> H_REQ#4 REQ[4]# H_HIT#
<7> H_A#[17..35] HIT# G6 H_HIT# <7>
H_A#17 Y2 E4 H_HITM#
C H_A#18 A[17]# HITM# H_HITM# <7> C
U5 A[18]#
H_A#19 R3 AD4
A[19]# BPM[0]#
ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]# +3VS
U4 AD1
H_A#22 Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4 Thermal Sensor EMC1402-1-ACZL-TR
XDP/ITP SIGNALS
H_A#23 U1 AC2
H_A#24 A[23]# PRDY#
R4 A[24]# PREQ# AC1
0.1U_0402_16V4Z
H_A#25 T5 AC5 XDP_TCK 1
H_A#26 A[25]# TCK XDP_TDI
T3 AA6
H_A#27 A[26]# TDI XDP_TDO C13
W2 AB3 T84
H_A#28 A[27]# TDO XDP_TMS
W5 AB5
H_A#29 A[28]# TMS XDP_TRST# 2
Y4 AB6
H_A#30 A[29]# TRST# XDP_DBRESET# U2
U2 C20 XDP_DBRESET# <19>
H_A#31 A[30]# DBR# EC_SMB_CK2
V4 1 8 EC_SMB_CK2 <16,27,31>
H_A#32 A[31]# VDD SCLK
W3
H_A#33 A[32]# H_THERMDA EC_SMB_DA2
AA4
A[33]# THERMAL 2
D+ SDATA
7 EC_SMB_DA2 <16,27,31>
H_A#34 AB2 H_PROCHOT# R146 68_0402_1%~D +VCCP C5
H_A#35 A[34]# H_THERMDC
AA3 D21 1 2 3 6
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA_R R57 H_THERMDA D- ALERT#
<7> H_ADSTB#1 V1
ADSTB[1]# THERMDA
A24 1 2 100_0402_5% 2200P_0402_50V7K
B25 H_THERMDC_R R53 1 2 100_0402_5% H_THERMDC L_THERM# 4 5
H_A20M# THERMDC THERM# GND
<18> H_A20M# A6
A20M#
ICH
H_FERR# A5 C7 H_THERMTRIP# R16
<18> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <7,18>
H_IGNNE# C4 +3VS 1 2 EMC1402-2-ACZL-TR MSOP 8P
<18> H_IGNNE# IGNNE#
H_THERMDA, H_THERMDC routing together, 10K_0402_5%
H_STPCLK# D5 Address:100_11000
<18> H_STPCLK# H_INTR STPCLK# Trace width / Spacing = 10 / 10 mil
<18> H_INTR C6
LINT0 H CLK
H_NMI B4 A22 CLK_CPU_BCLK
<18> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <15>
H_SMI# A3 A21 CLK_CPU_BCLK#
<18> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <15>
C76
M4
N5
RSVD[01] FAN Control circuit 10U_1206_16V4Z~N
2 1
RSVD[02] +5VS
T2
B RSVD[03] C88 B
V3
RSVD[04] 1000P_0402_50V7K~N
B2 1 2
RESERVED
RSVD[05] C77 10U_1206_16V4Z~N
D2 2 1
RSVD[06]
D22
RSVD[07] U3
D3
RSVD[08]
F6 1 8
RSVD[09] VEN GND
2 7
FAN1_POWER VIN GND
3 6
EN_DFAN1 VO GND
<27> EN_DFAN1 4 5
VSET GND
Penryn +3VS RT9027BPS SO 8P
1
JFAN1
R61
40mil
1
+VCCP 10K_0402_5% 1
2
2
3
3
2
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