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A B C D E
1 1
2
Blue Moutain KIWB1/B2 2
Schematics Document
Mobile Penryn uFCPGA with Intel
3
Cantiga_GM/PM+ICH9-M core logic 3
REV:2.0
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4602P
Date: Wednesday, March 18, 2009 Sheet 1 of 53
A B C D E
A B C D E
ZZZ1
Compal confidential POWER BD Slide Bar LED X 10 (B) RIGHT BD
File Name : Power on X1 USER-DEFINED (W) VOLUME UP X1
LED X1 (G) DOLBY (W) VOLUME DOWN X1
15.6W_PCB_LA4601P
:POWER LED X 3 MUTE X1
NOVO X1 WIRELESS LED (G) MUTE LED X1(G)
VRAM 64*16 Mobile Penryn BLUETOOTH LED (G)
1
DDR3*8 3G LED (G) 1
page20
uFCPGA-478 CPU Clock Gen. HDD LED (G) USB_Board
PCI-E X16 SLG8SP556VTR
NVidia N10M-GS1 USB CONN X 2
ICS9LPRS387AKLFT POWER ON (G) TV CONN X1
page5,6,7 page25
NVidia N10P-GE1 BATTERY CHARG(G/A)
page16~24 WIRELESS SWITCH (G)
H_A#(3..35) FSB ON/OFF
H_D#(0..63) 667/800/1066MHz
Double check ME
HDMI PS8101T PCI-E DDR3-800(1.5V)
CONN
page26 DDR3-SO-DIMM X2
page26
Intel Cantiga GMCH DDR3-1067(1.5V) BANK 0, 1, 2, 3 page 14,15
CRT cable PCBGA 1329 Dual Channel UP TO 8G
LVDS I/F
page28
page 8,9,10,11,12,13
SPK amplifier 2Channel Speaker
2
page36 page37 2
LVDS
Connector page27 DMI C-Line WOOFER amplifier 1Channel Speaker
page37
page37
PCI Express AZALIA Audio Codec
6*PCI-E BUS Realtek ALC272 HP X 1+
Mini card Slot 1
page31
Intel ICH9-M 12*USB2.0
page36
MIC_Ext X1 page37
None mBGA-676
PCI Express PCI BUS 2Channel MIC_Int
4*SATA serial page36
New Card CMOS Camera
Mini card Slot 2 page31 3.3V / 33 MHz page27,28,29,30
page41
page31
PCI Express BlueTooth CONN
LPC BUS page41
Mini card Slot 3
3
page31 USB CONN X1 3
page41
BCM5906/BCM5784M
EC
ENE KB926D New Card X1
SIM Card 10/100/1G LAN page38 page31
page32
page31 Realtek 5158E
M-PCIE CONN X 3 MS/MS
page31
pro/SD/SD
RJ45 CONN Int.KBD pro/mmc/XD page36
page33 page39
Touch Pad BIOS
page39
page40 REPEATER ESATA HDD AND USB CONN
page35 page35
HDD/ODD,SCL & T/L LED on MB SATA HDD CONN
4 CAPS and NUM on KBD page35 4
SATA ODD CONN
page35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/16 Deciphered Date 2010/03/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4602P
Date: Wednesday, March 18, 2009 Sheet 2 of 53
A B C D E
A B C D E
DDR3 Voltage Rails
+5VS
+3VS
+1.5VS
power
plane +1.1VS SMBUS, SPI and I2C Control Table
+VCCP
1 1
+5VALW +1.5V +CPU_CORE SERIAL NEW CLK CAP Mini Mini THERMAL THERMAL
SOURCE HDMI LVDS CRT HDCP EEPROM BATT SENSOR SENSOR
+B +VGA_CORE CARD GEN sensor CARD1 CARD2 (VGA) (CPU)
+3VALW +1.8VS
+0.75V
EC_SMB_CK1
EC_SMB_DA1
KB926 X X X X X X X X X X V X X
State
EC_SMB_CK2
EC_SMB_DA2
KB926 X X X X X X X V X X X V V
ICH_SMBCLK
ICH_SMBDAT ICH9 X X X X X V V X V V X X X
LVDS_SCL
LVDS_SDA Cantiga
X V X X X X X X X X X X X
S0
O O O O GMCH_CRT_CLK
GMCH_CRT_DAT Cantiga
X X V X X X X X X X X X X
HDMICLK_NB
S3
O O O X HDMIDAT_NB Cantiga
V X X X X X X X X X X X X
2
S5 S4/AC
O O X X
VGA_DDCCLK
VGA_DDCDATA VGA X X V X X X X X X X X X X 2
S5 S4/ Battery only
O X X X
VGA_LVDS_SCL
VGA_LVDS_DAT VGA X V X X X X X X X X X X X
VGA_HDMI_SCL
S5 S4/AC & Battery
don't exist X X X X VGA_HDMI_DAT VGA
V X X X X X X X X X X X X
HDCP_SMB_CK1
HDCP_SMB_DA1 VGA X X X X V X X X X X X X X
@ FUNCTION FSEL#SPICS#_SB
FRD#SPI_SO_SB
SPI_CLK_SB ICH9 X X X X V X X X X X X X X
FWR#SPI_SI_SB
100@ (100 LAN) FSEL#SPICS#
TVSW@ (TV POWER SW) 10M@ (N10M 40nm CHIPSET)
FRD#SPI_SO
SPI_CLK
FWR#SPI_SI
KB926 X X X X V X X X X X X X X
AO@ (ALWAYS ON SW) 10P@ (N10P 40nm CHIPSET)
MONO@ (MONO MIC) PM@ (VGA BOM)
3 3
X76@ (X76 BOM) 45@ (45 BOM)
GM@ (UMA BOM)
GM45@ (GM45 BOM)
GL40@ (GL40 BOM)
BT@ WITH BLUETOOTH GIGA@ (GIGA LAN)
3G@ WITH 3G NO_TVSW@ (NON TV POWER SW)
TV@ WITH TV NO_AO@ (NON ALWAY ON SW)
ARRAY@ (ARRAY MIC)
S512@ FOR X76 BOM
Q512@ FOR X76 BOM
4
S256@ FOR X76 BOM 4
Q256@ FOR X76 BOM
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Wednesday, March 18, 2009 Sheet 3 of 53
A B C D E
A B C D E
VGA and DDR3 Voltage Rails (N10x GPIO) Performance Mode P0 TDP at Tj = 102 C* (DDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 N/A N/A Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO1 IN - Hot plug detect for IFP link C N10P-GS
128bit 21.07 6.67 TBD TBD 18.25 17.34 2.06 3.09 4.09 6.14 850 0.89 75 0.14 63 0.07 55 0.18
1024MB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) DDR3
1 1
GPIO3 OUT H Panel Power Enable N10P-GE
128bit 20.97 6.73 TBD TBD 19.17 17.25 2.03 3.05 4.09 6.14 840 0.88 75 0.14 63 0.07 55 0.18
1024MB
GPIO4 OUT H Panel Back-Light On/Off (PWM) DDR3
GPIO5 OUT - GPU VID0 N10P-LP
128bit 15.48 6.44 TBD TBD 13.95 11.86 1.90 2.85 3.99 5.99 810 0.85 75 0.14 63 0.07 55 0.18
1024MB
GPIO6 OUT - GPU VID1 DDR3
GPIO7 OUT - GPU VID2
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO8 I/O L Thermal Catastrophic Overtemp
FBVDDQ PCI Express I/O and I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
GPIO9 OUT L Thermal Alert (4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO10 OUT Memory VREF switch
N10M-GE
GPIO11 I/O L SLI raster sync 64bit 13.36 2.93 TBD TBD 11.89 10.70 0.66 0.99 2.16 3.24 792 0.83 75 0.14 63 0.07 100 0.33
512MB
DDR3
GPIO12 IN - AC power detect pin
N10M-GS
2
GPIO13 OUT - MEM_VID orPower supply control 64bit 14.29 3.10 TBD TBD 11.53 11.53 0.70 1.05 2.28 3.42 817 0.86 75 0.14 63 0.07 100 0.33 2
512MB
DDR3
GPIO14 OUT - Power supply control
N10M-LP
GPIO15 IN - Hot plug detect for IFP Link E 64bit 8.28 2.91 TBD TBD 6.60 5.61 0.62 0.93 2.20 3.3 782 0.82 75 0.14 63 0.07 100 0.33
512MB
DDR3
GPIO16 OUT - Programmable Fan Control
GPIO17 IN - The ramp time for any rail must be more than 40us
Power Sequence
GPIO18 IN -
GPIO19 IN - Hot plug detect for IFP Link D
GPIO20 IN - (+3VS) VDD33
GPIO21 IN - Hot plug detect for IFP link F
PEX_VDD can ramp up any time
GPIO22 IN - SLI swap ready signal
(1.1VS) PEX_VDD
GPIO23 I/O
tNVVDD
3 3
(+VGA_CORE) NVVDD
GPIO6 GPIO5 N10M-GS N10P-GS
GPU_VID1 GPU_VID0 VGA_CORE P-State tNV-IFPAB_IOVDD
0 0 0.8V 12
0 1 0.85V 12 IFPAB_IOVDD
1 1 0.9V 0, 10
tNV-FBVDDQ
(1.8VS) FBVDDQ
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4602P
Date: Wednesday, March 18, 2009 Sheet 4 of 53
A B C D E
5 4 3 2 1
XDP Reserve
+VCCP +3VS
H_IERR# R1 1 2 56_0402_5% XDP_DBRESET# R2 1 2 @ 1K_0402_5%
H_PROCHOT# R3 1 2 56_0402_5%
+VCCP
XDP_TDI R4 1 2 54.9_0402_1%
USE->68 ,NOT USE-->56
D XDP_TMS R5 1 2 54.9_0402_1% D
CONN@
JCPU1A XDP_TDO R6 1 2 @ 54.9_0402_1%
H_A#3 J4 H1 H_ADS#
<8> H_A#[3..16] A[3]# ADS# H_ADS# <8>
ADDR GROUP_0
ADDR GROUP_0
H_A#4 L5 E2 H_BNR# XDP_TRST# R7 1 2 54.9_0402_1%
A[4]# BNR# H_BNR# <8>
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# <8>
H_A#6 K5 XDP_TCK R8 1 2 54.9_0402_1%
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# <8>
H_A#8 N2 F21 H_DRDY#
A[8]# DRDY# H_DRDY# <8>
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# <8>
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <8>
H_A#12 P2 A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# <28>
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# <8>
H_ADSTB#0 M1
<8> H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# <8>
H_REQ#0 K3 F3 H_RS#0
<8> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <8>
H_REQ#1 H2 F4 H_RS#1
<8> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <8>
H_REQ#2 K2 G3 H_RS#2
<8> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <8>
H_REQ#3 J3 G2 H_TRDY#
<8> H_REQ#3 REQ[3]# TRDY# H_TRDY# <8>
H_REQ#4 L1
<8> H_REQ#4 REQ[4]#
G6 H_HIT#
HIT# H_HIT# <8>
H_A#17 Y2 E4 H_HITM#
<8> H_A#[17..35] A[17]# HITM# H_HITM# <8>
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4
+3VS +3VS
ADDR GROUP_1
ADDR GROUP_1
H_A#20 W6 AD3 XDP_BPM#1
C H_A#21 A[20]# BPM[1]# XDP_BPM#2 C
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4 XDP_BPM#3
A[22]# BPM[3]#
1
H_A#23 U1 AC2 XDP_BPM#4
XDP/ITP SIGNALS
A[23]# PRDY# 1
H_A#24 R4 AC1 XDP_BPM#5
H_A#25 A[24]# PREQ# XDP_TCK C1 U1 @ R9
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI 0.1U_0402_16V4Z 10K_0402_5%
H_A#27 A[26]# TDI XDP_TDO 2
W2 AB3
2
H_A#28 A[27]# TDO XDP_TMS EC_SMB_CK2
W5 A[28]# TMS AB5 1 VDD SMCLK 8 EC_SMB_CK2 <16,38,42>
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET# H_THERMDA EC_SMB_DA2
U2 A[30]# DBR# C20 XDP_DBRESET# <29> 2 DP SMDATA 7 EC_SMB_DA2 <16,38,42>
H_A#31 V4
H_A#32 A[31]# H_THERMDC
W3 A[32]# 1 2 3 DN ALERT# 6
H_A#33 AA4 THERMAL C2 2200P_0402_50V7K
H_A#34 A[33]# H_PROCHOT# THERM#
AB2 A[34]# 4 THERM# GND 5
H_A#35 AA3 D21
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA
<8> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC +3VS 1 2
H_A20M# THERMDC R10 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
<28> H_A20M# A6 A20M#
ICH
ICH
H_FERR# A5 C7 H_THERMTRIP#
<28> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,28>
H_IGNNE# C4
<28> H_IGNNE# IGNNE#
<28> H_STPCLK#
H_STPCLK# D5 STPCLK#
2nd Source: ADT7421ARMZ (SA00001UN00)
H_INTR C6 H CLK
<28> H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
<28> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <23>
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