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A B C D E
1 1
Compal confidential
2
Liverpool/Sunderland 10AT 2
NSWAE/NTWAE LA-5332P Schematics Document
Mobile AMD S1G3/
RS880M & RS880MC / SB710
3 3
2009-11-24 Rev. 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
2009-02-12 2009-02-12 Title
Issued Date Deciphered Date Schematic, MB LA-5332P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, February 05, 2010 Sheet 1 of 45
A B C D E
A B C D E
Compal Confidential
A M D S1G3 C P U T h e r m al S e n s o r F a n C o n tr o l
M o d el N a m e : N S W A E & N T W A E U M A
uFCPGA-638 Package ADM1032ARMZ page 7 APL5607KI-TRG page 5
F il e N a m e : L A - 5 3 3 2 P
T i g ris P l a tf o r m page 5,6,7,8
1 H y p e r T r a n s p o rt L i n k 2 . 6 G H z 1
16X16
2 0 0 p i n D D R II- S O - D I M M X 2
C R T C o n n.
page 17 A TI BANK 0, 1, 2, 3 page 9,10
RS880M
M e m o r y B U S D D R II
L C D C o n n. RS880MC D u al C h a n n el
page 17
1 . 8 V D D R II 6 6 7 / 8 0 0 M H Z
H D M I C E C C o n tr o ll e r H D M I C o n n.
EC SMBUS
R5F211B4D33SP page 19 page 19
2
PCIe 4x 1.5V 2.5GHz(250MB/s) page 11,12,13,14,15 2
A - L i n k E x p r e s s II
4 X P C I- E
R ig h t U S B C o n n I n t. C a m e r a B lu e t o o t h
USB Port 0,1 page 32 USBPort 9 page 17 USBPort 6 page 32
A TI
R T L 8 1 0 3 E L L A N 1 0/1 0 0 M P C I e M ini C a r d W L A N N E W C ard USB 5V 480MHz
SB710 USB 5x
USB port 5
PCIe port 3 page 26 PCIe Port 2 page 27 5V 480MHz
PCIe port 0 page 27
SATA 5V 1.5GHz(150MB/s) W LA N F i n g e r P ri n t e r R T S5159 V D D 3IN1
R J45 eSATA USBPort 8 page 27 USBPort 7 page 32 USBPort 4 page 29 page 29
page 26 USB port 2
USB 5V 480MHz
SATA port 2 page 25
PCI BUS 3.3V 33 MHz
SATA
SATA HDD1
SATA port 1 page 25
3
5V 1.5GHz(150MB/s) 3
C a r d B u s C o n tr o ll e r SATA
SATA O DD
OZ601 page 28 page 20,21,22,23,24 SATA port 3 page 25
C lo c k G e n e r a t o r P o w e r/ B 5V 1.5GHz(150MB/s)
SLG8SP626VTR page 16 page 35 LPC BUS 3.3V 33 MHz
R T C C K T. U S B/B HD Audio 3.3V 24.576MHz/48Mhz
page 37 page 32
D e b u g P o rt E N E K B926 D 3
page 33 page 34
P o w e r O n / O ff C K T O D D/B M D C 1.5 H D A C odec
page 35 page 25 page 33 ALC272 page 30
I n t. K B D S PI R O M
D C / D C I n t e rf a c e C K T T o u c h P a d/ B page 33 page 33
page 36 page 35
R J11 A M P LI F I E R M IC C O N N I n t. M I C HP CONN V o l u m e C o n tr o l
page 33 TPA6017 page 31 page 31 page 31 page 31
page 31
P o w e r C ir c u it D C / D C
page 37,38,39,40,41,42,43
4 SPK CONN 4
page 31
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 2 of 45
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL
DESIGN CURRENT 0.1A +5VL
B+
TPS51125RGER DESIGN CURRENT 1A +3VALW
DESIGN CURRENT 3.5A +5VALW
D SUSP D
N-CHANNEL DESIGN CURRENT 2A +5VS
SI4800
SUSP
N-CHANNEL DESIGN CURRENT 1.5A +3VS
SI4800
ENVDD
P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
AO-3413
NSWAE Liverpool AMD SUSP
NTWAE Sunderland AMD DESIGN CURRENT 1.5A +1.5VS
APL5331KAC
BT_PWR#
C DESIGN CURRENT 180mA C
P-CHANNEL +BT_VCC
AO-3413
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
DESIGN CURRENT 300mA +2.5VS
APL5508
POK
DESIGN CURRENT 0.3A +1.2VALW
TPS51117RGYR
VLDT_EN#
N-CHANNEL DESIGN CURRENT 4.5A +1.2V_HT
IRF8113
VR_ON
B DESIGN CURRENT 18A B
+CPU_CORE0
DESIGN CURRENT 18A +CPU_CORE1
ISL6265
DESIGN CURRENT 3A +VDDNB
SYSON
DESIGN CURRENT 7A +1.8V
TPS51117RGYR
SUSP
N-CHANNEL DESIGN CURRENT 1A +1.8VS
IRF8113
SYSON#
DESIGN CURRENT 2A +0.9V
APL5331KAC
A A
SUSP#
DESIGN CURRENT 7A +NB_CORE
TPS51117RGYR
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 3 of 45
5 4 3 2 1
A B C D E
@ : just reserve , no build Platform CPU NB VGA SB Comment
Voltage Rails
DEBUG@ : reserve for debug. S1G3 RS880MC NA SB710
O : ON S1G3 RS880M NA SB710
X : OFF
BTO (Build-To-Order) Option Table
+5VS Function Express card / PCMCIA BLUE TOOTH RJ11 SSD SATA ODD WiFi HDMI G- sensor 3 in 1 card reader FingerPrinter CAMERA & MIC
1
+3VS 1
power Description (E/A) (B) (R) (H) (Y) (S) (C) (F) (X)
plane +2.5VS
+1.8VS Explain 16" 17" Half - size First Second RTS5159 CAMERA MIC
+1.5VS
BTO EXPCARD@ / PCMCIA@ BT@ MDC@ SSD@ 16inch@ 17inch@ WLAN@ H@ G@ + G_1st@ G@ + G_2nd@ CARD@ FP@ CAM@ MIC@
+1.1VS
+B +5VALW +1.8V
+VGA_CORE
+3VL +3VALW +0.9V
+1.2V_HT Function DC-IN Side port
+5VL +1.2VALW +0.9V
State +CPU_CORE_NB
+RTCVCC +3V_LAN Description (L)
+CPU_CORE_0
+CPU_CORE_1 Explain
BTO 16inch_45@ 17inch_45@ SIDE@ NSIDE@
S0 O O O O
S1 O O O O
2 2
S3 O O O X
S5 S4/AC O O X X
S5 S4/ Battery only O X X X
SMBUS Control Table
S5 S4/AC & Battery
don't exist X X X X CPU LCD HDMI
SOURCE INVERTER BATT HDMI SODIMM CLK WLAN DDC DDC NEW
CEC THERMAL GEN CARD
I / II ROM ROM
SENSOR
EC_SMB_CK1
KB926
I2C / SMBUS ADDRESSING EC_SMB_DA1 V V
EC_SMB_CK2
KB926
EC_SMB_DA2 V
DEVICE HEX ADDRESS
I2C_CLK
RS880M
3
DDR SO-DIMM 0 A0 10100000 I2C_DATA V 3
DDR SO-DIMM 1 A2 10100010 DDC_CLK0
RS880M
CLOCK GENERATOR (EXT.) D2 11010010 DDC_DATA0 V
DDC_CLK1
RS880M
DDC_DATA1
SCL0
SB710
SDA0 V V V
EC SM Bus1 address EC SM Bus2 address SCL1
SB710
SDA1 V
Device HEX Address Device HEX Address
SCL2
Smart Battery 16H 0001 011X b ADI1032-1 CPU 98H 1001 100X b SB710
SDA2
HDMI-CEC 34H 0011 010X b ADI1032-2 VGA 9AH 1001 101X b
SCL3
EC KB926D3 EC KB926D3 SB710
SDA3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 4 of 45
A B C D E
A B C D E
+1.2V_HT
250 mil VLDT CAP. Near CPU Socket
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
10U_0805_10V6K 10U_0805_10V6K 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
1 1
H_CADIP[0..15] H_CADOP[0..15]
11 H_CADIP[0..15] H_CADOP[0..15] 11
H_CADIN[0..15] H_CADON[0..15]
11 H_CADIN[0..15] H_CADON[0..15] 11
+1.2V_HT JCPUA
C7
D1 HT LINK AE2 +VLDT_B 1 2 10U_0805_10V6K < VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT_A0 VLDT_B0
VLDT=500mA D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
2 H_CADIP4 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H_CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
< From NB > F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 < To NB >
H_CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H_CADIN12 K4 W5 H_CADON12
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
H_CADIN13 M5 V3 H_CADON13
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
H_CADIN14 M4 U5 H_CADON14
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15
11 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 11
11 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 11
11 H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 11
11 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 11
11 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 11
11 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 11
3 3
11 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 11
11 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 11
@ 6090022100G_B
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
1
D1
2 @
+FAN1 C183 1SS355_SOD323-2
JFAN +3VS
1
2
C192 10U_0805_10V4Z +FAN1 1
1 1
2 2
1
1
10U_0805_10V4Z 1 3
2 U6 D2 C9 3 R12
1 8 @ @ 4
EN GND BAS16_SOT23-3 1000P_0402_50V7K GND 10K_0402_5%
2 VIN GND 7 5 GND
2
3 6
2
2
VOUT GND @ ACES_85204-0300N
< From EC > 34 EN_DFAN1 4 VSET GND 5 FAN_SPEED1 34 < To EC >
4 4
2
APL5607KI-TRG_SO8 C8
@
0.01U_0402_25V7K
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 5 of 45
A B C D E
A B C D E
< DDR2 VREF is 0.5 ratio > < PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH > < Processor DDR2 Memory Interface >
+1.8V
DDR_A_CLK0 DDR_B_CLK0
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