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>> Download Compal_LA-5754P documenatation << Text preview - extract from the document A B C D E
1 1
Compal Confidential
2 2
NAWE6 Schematics Document
AMD Danube
Champlain Processor with RS880M/SB820/Park VGA
3
2010-02-24 3
LA5754 REV: 0.2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE6 LA-5754P
Date: Monday, March 01, 2010 Sheet 1 of 47
A B C D E
A B C D E
Compal Confidential ZZZ1 ZZZ2
CAP SENSOR BD: CARD READER BD:
POWER BD: ZZZ3
ZZZ4
Model Name : AMD Danube + Park VOLUME UP
POWER BTN RTS5159
LA5754P LS-5758P 4 layer
VOLUME DOWN
NOVO BTN HP JACK
MUTE
DAZ@
@ POWER MANAGE BTN LS5756P MIC JACK
DA40000TD00
@
AUDIO ENHANCE LS5753P
DA80000IP00 DA40000T300 BUTTON & LED @
DA40000Q210
1
Danube 1
VRAM 512MB
64M16 x 4 AMD S1G4 Processor
page 18 Memory BUS(DDR3) 204pin DDRIII-SO-DIMM X2
uPGA-638 Package Dual Channel BANK 0, 1, 2, 3 page 8,9
DDR3 Champlain page 4,5,6,7 1.5V DDRIII 800~1333MHz
ATI M93-S3
Park - S3 Hyper Transport Link
uFCBGA-631 PCI-Express x 16 16 x 16
Page 13,14,15,16,17
Gen2 Thermal Sensor Clock Generator
ATI RS880M
ADM1032 ICS9LPRS488
page 6 page 19
LVDS uFCBGA-528
page 27
2 2
page 10,11,12,13 page 37 page 37 page 27 page 37 page 28 page 28 page 28
CRT
page 25
A link Express2 USB USB CMOS Bluetooth Mini 3G/GPS
Gen1 PORT conn Camera Conn card WWAN New Card
HDMI Conn. (LEFT) (Right) (WL)X1
page 26 USB port 0 USB port 12 USB port 5 USB port 6 USB port 11 USB port 10 USB port 7
ATI SB820M 3.3V 48MHz USB
S-ATA Gen2
LAN(GbE) uFCBGA-605
New Card 3G/WWAN MINI Card Atheros 3.3V 24.576MHz/48Mhz
WLAN WLAN page 20,21,22,23,24
MINI Card AR8151/8152
page 28 page 28 page 28 page 29
HD Audio ESATA &
GPP3 GPP2 GPP1 GPP0 SATA HDD CDROM
USB
SIM RJ45 Conn. page 32 Conn. 32
page Combine CON
3 3
Card page 30 LPC BUS port 0 port 1 USB port 4
page28 page28
LED USB(WWAN)
page 36
USB port 2
Audio Codec Card Reader /
ENE KB926
LID SW / IO BD page 34
Realtec ALC259 Audio Jack SB CONN
page33
page 32 RTS5159-GR
HP X 1+
MS/MS
MIC_Ext X1
pro/SD/SD
Power On/Off CKT. Touch Pad Int.KBD pro/mmc/XD page38
page 35 page 35
page 32 Analog 2Channel
MIC_Int Speaker
BIOS page33 page33
DC/DC Interface CKT. Fan Control page 34
page 31
4 4
page 38
Power Circuit
page 39,40,41,42,43,
Security Classification Compal Secret Data Compal Electronics, Inc.
44,45,46,47,48,49 Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE6 LA-5754P
Date: Monday, March 01, 2010 Sheet 2 of 47
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Voltage Rails
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE_0 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V) ON OFF OFF
+0.75VS +0.75VS LDO power rail for DDR3 VTT ON ON OFF
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF
SIGNAL
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V for CPU_VDDA ON OFF OFF S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VALW 3.3V always on power rail ON ON ON*
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON ON
+3VS 3.3V switched power rail ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON*
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VS 5V switched power rail ON OFF OFF
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
EC SM Bus1 address EC SM Bus2 address
3 3
Device Address HEX Device Address HEX
Smart Battery 0001 011X b 16H EMC1402-1 (CPU) 100_1100b 4CH
EMC1412-A (GPU) 111_1100b 7CH
EMC1403-2 (DDR,WWAN) 100_1101b 4DH
SB820 SB820 BOM Config
SM Bus 0 address SM Bus 1 address UMA only SKU: UMA@
Device Address HEX Device Address
DIS ONLY (Park S3): DIS@
EXT CLK Mode:EXT@
Clock Generator 1101 001Xb D2
(SILEGO SLG8SP626)
INT CLK mode:INT@
DDR DIMM1 1001 000Xb
LAN GIGA: 8151@
90
DDR DIMM2 1001 010Xb LAN 100: 8152@
94
CMOS@
BT@
4 4
3G@
S@
H@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE6 LA-5754P
Date: Monday, March 01, 2010 Sheet 3 of 47
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1 1
+1.1VS
VLDT CAP.
250 mil
2 2 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
[10] H_CADIP[0..15] H_CADOP[0..15] [10]
10U_0805_10V4Z 10U_0805_10V4Z
H_CADIN[0..15] H_CADON[0..15] 1 1 2 2 2 2
[10] H_CADIN[0..15] H_CADON[0..15] [10]
Near CPU Socket
+1.1VS +1.1VS
JCPU1A
C7
2
TBD 2
D1 VLDT_A0 HT LINK VLDT_B0 AE2 2 1
D2 VLDT_A1 VLDT_B1 AE3
D3 AE4 10U_0805_10V4Z
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 AC3
H_CADIP2 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP2
G3 AB1
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 AA1
H_CADIP3 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP3
G1 AA2
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 U1
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 U2
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 U3
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 T1
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 R1
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 AD4
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 AC5
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 AB5
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
3 H_CADIN13 H_CADON13 3
M5 V3
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 V5
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15
[10] H_CLKIP0 J3 Y1 H_CLKOP0 [10]
L0_CLKIN_H0 L0_CLKOUT_H0
[10] H_CLKIN0 J2 W1 H_CLKON0 [10]
L0_CLKIN_L0 L0_CLKOUT_L0
[10] H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 [10]
[10] H_CLKIN1 K5 Y3 H_CLKON1 [10]
L0_CLKIN_L1 L0_CLKOUT_L1
[10] H_CTLIP0 N1 R2 H_CTLOP0 [10]
L0_CTLIN_H0 L0_CTLOUT_H0
[10] H_CTLIN0 P1 R3 H_CTLON0 [10]
L0_CTLIN_L0 L0_CTLOUT_L0
[10] H_CTLIP1 P3 T5 H_CTLOP1 [10]
L0_CTLIN_H1 L0_CTLOUT_H1
[10] H_CTLIN1 P4 R5 H_CTLON1 [10]
L0_CTLIN_L1 L0_CTLOUT_L1
FOX_PZ6382A-284S-41F_Champlian
ME@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G4 HT I/F
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE6 LA-5754P
Date: Monday, March 01, 2010 Sheet 4 of 47
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Processor DDR3 Memory Interface
JCPU1C
[9] DDRB_SDQ[63..0]
MEM:DATA
DDRA_SDQ[63..0] [8]
DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.5V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
A11 F12
DDRB_SDQ2 MB_DATA1 MA_DATA1 DDRA_SDQ2
A14 H14
DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2
DDRB_SDQ4 G11 H11 DDRA_SDQ4
R1 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 H12
1K_0402_1% DDRB_SDQ6 MB_DATA5 MA_DATA5 DDRA_SDQ6
D12 MB_DATA6 MA_DATA6 C13
DDRB_SDQ7 A13 E13 DDRA_SDQ7
DDRB_SDQ8 MB_DATA7 MA_DATA7 DDRA_SDQ8
A15 H15
1
MEM_VREF DDRB_SDQ9 MB_DATA8 MA_DATA8 DDRA_SDQ9
A16 E15
MB_DATA9 MA_DATA9
1000P_0402_50V7K
0.01U_0402_25V7K
DDRB_SDQ10 A19 E17 DDRA_SDQ10
MB_DATA10 MA_DATA10
2
1 1 DDRB_SDQ11 A20 H17 DDRA_SDQ11
R2 DDRB_SDQ12 MB_DATA11 MA_DATA11 DDRA_SDQ12
C14 MB_DATA12 MA_DATA12 E14
C9
C8
1K_0402_1% DDRB_SDQ13 D14 F14 DDRA_SDQ13
DDRB_SDQ14 MB_DATA13 MA_DATA13 DDRA_SDQ14
C18 MB_DATA14 MA_DATA14 C17
2 2 DDRB_SDQ15 DDRA_SDQ15
D18 G17
1
DDRB_SDQ16 MB_DATA15 MA_DATA15 DDRA_SDQ16
D20 MB_DATA16 MA_DATA16 G18
DDRB_SDQ17 A21 C19 DDRA_SDQ17
DDRB_SDQ18 MB_DATA17 MA_DATA17 DDRA_SDQ18
D24 MB_DATA18 MA_DATA18 D22
DDRB_SDQ19 C25 E20 DDRA_SDQ19
DDRB_SDQ20 MB_DATA19 MA_DATA19 DDRA_SDQ20
B20 MB_DATA20 MA_DATA20 E18
DDRB_SDQ21 C20 F18 DDRA_SDQ21
DDRB_SDQ22 MB_DATA21 MA_DATA21 DDRA_SDQ22
B24 MB_DATA22
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