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A B C D E
1 1
Compal Confidential
2
Schematics Document 2
INTEL Auburndale BGA with IBEX core logic
Fossil 2.0 UMA
LA-6161P
3 3
2010-05-24
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2009/09/03 Title
SCHEMATICS, MB A6161
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401860 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 29, 2010 Sheet 1 of 41
A B C D E
A B C D E
Compal Confidential
File Name : LA-6161P Fossil 2.0 UMA XDP Conn.
Page 4
Accelerometer
LIS302DLTR
DDR3 1066/1333MHz 1.5V DDR3-SO-DIMM X 1
Mobile BANK 2, 3 Page 9 Page 22
1 Single Channel 1
Arrandale CPU Fan Control
Page 4
BGA 1288pins
Page 4,5,6,7,8
LVDS
Page 18
Display port DDI_D FDI DMI X4
Page 17
BT(SoftBreeze) Conn USB x 1
page 26
CRT
Page 19 USB conn x 3(For I/O)
DDI daughter board
page 24
2 2
USB2.0
WWAN CardReader Controller
+SIM Card
USB2.0
Intel Ibex Peak M SD/MMC Slot
USB*1 Azalia RealTek RTS5159
Page 22
PCI-E BUS 1071pins
sub/B Page 3
25mm*27mm
SATA0
USB x1(Camara)
Page 18
10/100/1000 LAN WLAN Card
Page 11,12,13,14,15,16
RTL8151DH-GR FPR conn x1
PCIE*1 Page 19
Page 21 Page 22 ONFI Interface
daughter board
RJ45 CONN Audio CKT
3 IDT 92HD80 Page 23 Audio Jack sub/B Page 2 3
Page 21
SATA HDD Connector
SPI BUS Page 19
RTC CKT. LED
Page 11 LED Board
SMSC KBC 1098
Page 20 page 28
Power OK CKT.
Page 29
Touch Pad CONN. Int.KBD CK505
Page 25
Page 25
Clock Generator
4 SLG8SP585VTR 4
Power On/Off CKT. SPI BUS
Page 25 SPI ROM 4MB Page 11
MX25L6445EM2I-10G Page 27
Security Classification Compal Secret Data Compal Electronics, Inc.
2008/09/15 2009/09/03 Title
DC/DC Interface CKT. Issued Date Deciphered Date
SCHEMATICS, MB A6161
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Page 30 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401860 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 29, 2010 Sheet 2 of 41
A B C D E
A
( O MEANS ON X MEANS OFF )
Voltage Rails Symbol Note :
+RTCVCC +B +5VALW +1.5V +5VS
+3VL +3VALW +0.75V +3VS
+1.5VS
: means Digital Ground
power
plane +VCCP
+CPU_CORE
+1.05VS : means Analog Ground
+1.8VS
@ : means just reserve , no build
State ULV@ : means just install for ULV CPU
CONN@ : means ME part.
L Layout Notes
07/24 update
S0
O O O O O : Question Area Mark.(Wait check)
S1
O O O O O
S3
O O O O X Install below 45 level BOM structure for ver. 0.1
S5 S4/AC 45@ : means just put it in the BOM of 45 level.
O O O X X
S5 S4/ Battery only
O O X X X
S5 S4/AC & Battery
don't exist
O X X X X Install below 43 level BOM structure for ver. 0.1
1 1
Remove before MP
DEBUG@ : means just build when PCIE port 80 CARD function enable.
SMBUS Control Table
THERMAL
SOURCE BATT XDP SODIMM CLK CHIP MINI CARD DOCK NIC SENSOR G-SENSOR
SMB_EC_CK1
SMB_EC_DA1
SMSC1098 V X X X X X X X X
SMBCLK
SMBDATA
Calpella X V V V V V X X V
SML0CLK
SML0DATA
Calpella X X X X X X V X X
SML1CLK
SML1DATA
Calpella X X X X X X X V V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2009/09/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A6161
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401860 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 29, 2010 Sheet 3 of 41
A
1 2 3 4 5
Layout rule 10mil width trace
length < 0.5", spacing 20mil
U1B
20_0402_1% 1 R2 2 H_COMP3 AD71 COMP3 CLK_CPU_BCLK
BCLK AK7 CLK_CPU_BCLK <14>
Misc
20_0402_1% 1 R5 2 H_COMP2 AC70 AK8 CLK_CPU_BCLK#
COMP2 BCLK# CLK_CPU_BCLK# <14>
49.9_0402_1% 1 R7 2 H_COMP1 AD69 K71 CLK_CPU_XDP
COMP1 BCLK_ITP
Clocks
J70 CLK_CPU_XDP#
49.9_0402_1% 1 R9 H_COMP0 BCLK_ITP#
2 AE66 COMP0
L21 CLK_EXP
PEG_CLK CLK_EXP <12>
J21 CLK_EXP#
PEG_CLK# CLK_EXP# <12> +1.5V
PAD T48 TP_SKTOCC# M71 PROC_DETECT R1093
Y2 R46 0_0402_5%
A DPLL_REF_SSCLK CLK_DP <12> A
W4 1 @ 2 2 1
DPLL_REF_SSCLK# CLK_DP# <12>
H_CATERR# N61 CATERR# 1K_0402_5%
SM_DRAMRST# 1 6 DRAMRST# <9>
Thermal
Thermal
BJ12 SM_DRAMRST#
SM_DRAMRST#
<14> H_PECI 1 R14 2 H_PECI_ISO N19 PECI
Q52A
0_0402_5% BV33 SM_RCOMP0 2 R1092 1 2N7002DW-7-F_SOT363-6
2
SM_RCOMP[0] SM_RCOMP1
SM_RCOMP[1] BP39 PCH_DDR_RST <14>
to power; PU to VCCP at power side also BV40 SM_RCOMP2 @ 100K_0402_5%
SM_RCOMP[2]
DDR3
Misc
<37> H_PROCHOT# 1 R15 2 H_PROCHOT#_D N67 PROCHOT#
C6 1 2 470P_0402_50V7K
0_0402_5% AV66 PM_EXTTS#0 T49 PAD
PM_EXT_TS#[0] PM_EXTTS#1
PM_EXT_TS#[1] AV64 1 R16 2 PM_EXTTS#1_R <9>
0_0402_5% from DDR
<14> H_THERMTRIP# 1 R17 2 H_THERMTRIP#_R N17 THERMTRIP#
Intel S3 power reduction circuit for Calpella. 11/09
0_0402_5%
U71 XDP_PRDY# @ R1493 1 2 0_0402_5% XDP_PREQ#_R
PRDY# XDP_PREQ# @ R1494 0_0402_5% XDP_PRDY#_R
PREQ# U69 1 2
H_CPURST# @ 1 R18 2 H_CPURST#_R N70 T67 XDP_TCK
0_0402_5% RESET_OBS# TCK XDP_TMS reserve for ESD, Compal SI 1/19
TMS N65
Power Management
Power Management
<13> H_PM_SYNC 1 R19 2 H_PM_SYNC_R M17 PM_SYNC TRST# P69 XDP_TRST#
0_0402_5%
T69 XDP_TDI
TDI
TDO T71
P71
XDP_TDO
XDP_TDI_M
CPU XDP Connector
JTAG & MBP
H_CPUPWRGD TDI_M
1 R21 2 SYS_AGENT_PWROK AM7 VCCPWRGOOD_1 TDO_M T70 XDP_PREQ#_R JP4
0_0402_5% XDP_PRDY#_R 1 2
XDP_DBRESET# GND0 GND1
DBR# W71 3 OBSFN_A0 OBSFN_C0 4 CFG8 <5>
<14> H_CPUPWRGD 1 R22 2 VCCPWRGOOD_0 Y67 VCCPWRGOOD_0
XDP_BPM#0 R23 1 2 0_0402_5% 5 OBSFN_A1 OBSFN_C1 6 CFG9 <5>
0_0402_5% @ R24 1 2 0_0402_5% 7 8
<5> CFG12 GND2 GND3
J69 XDP_BPM#0 XDP_BPM#1 R25 1 2 0_0402_5% 9 10
B BPM#[0] OBSDATA_A0 OBSDATA_C0 CFG0 <5> B
<13> PM_DRAM_PWRGD 1 R26 2 VDDPWRGOOD_R AM5 SM_DRAMPWROK BPM#[1] J67 XDP_BPM#1
<5> CFG13
@ R27 1 2 0_0402_5% 11 OBSDATA_A1 OBSDATA_C1 12 CFG1 <5>
0_0402_5% J62 XDP_BPM#2 XDP_BPM#2 R28 1 2 0_0402_5% 13 14
from power BPM#[2] XDP_BPM#3 @ R29 0_0402_5% GND4 GND5
BPM#[3] K65 <5> CFG14 1 2 15 OBSDATA_A2 OBSDATA_C2 16 CFG2 <5>
<29> VTTPWRGOOD H15 K62 XDP_BPM#4 XDP_BPM#3 R30 1 2 0_0402_5% 17 18
VTTPWRGOOD BPM#[4] OBSDATA_A3 OBSDATA_C3 CFG3 <5>
J64 XDP_BPM#5 @ R31 1 2 0_0402_5% 19 20
BPM#[5] <5> CFG15 GND6 GND7 +3VS
K69 XDP_BPM#6 21 22
BPM#[6] <5> CFG17 OBSFN_B0 OBSFN_D0 CFG10 <5>
H_PWRGD_XDP 1 R32 2 H_PWRGD_XDP_R Y70 M69 XDP_BPM#7 ESD request to add 23 24
TAPPWRGOOD BPM#[7] <5> CFG16 OBSFN_B1 OBSFN_D1 CFG11 <5>
@ 0_0402_5% 25 26
R33 PLT_RST#_R XDP_BPM#4 0_0402_5% GND8 GND9
<14> BUF_PLT_RST# 1 2 G3 RSTIN# 1 2 R43 XDP_BPM#4_R 27 OBSDATA_B0 OBSDATA_D0 28 CFG4 <5>
2
XDP_BPM#5 0_0402_5% 1 2 R48 XDP_BPM#5_R 29 30
OBSDATA_B1 OBSDATA_D1 CFG5 <5>
1.5K_0402_1% 31 32 R34
GND10 GND11
1
+VCCP XDP_BPM#6 0_0402_5% 1 2 R40 XDP_BPM#6_R 33 34 1K_0402_5%
OBSDATA_B2 OBSDATA_D2 CFG6 <5>
XDP_BPM#7 0_0402_5% 1 2 R41 XDP_BPM#7_R 35 36
OBSDATA_B3 OBSDATA_D3 CFG7 <5>
R35 INTEL_AUBURNDALE_1288 1 37 38
1
750_0402_1% H_CPUPWRGD R36 2 H_CPUPWRGD_R GND12 GND13 CLK_CPU_XDP
1 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
C1 1K_0402_5% PM_PWRBTN#_R CLK_CPU_XDP# +VCCP
2nd Source : <13> PM_PWRBTN#_R 41 42
2
0.1U_0402_16V4Z HOOK1 ITPCLK#/HOOK5 @ 1K_0402_5%
43 44
SV - i5-540M CPU : 2.53G (K0) @ 2 H_PWRGD_XDP 1 R37 2 45
VCC_OBS_AB VCC_OBS_CD
46 XDP_RST#_R R38 1 2 H_CPURST#
0_0402_5% HOOK2 RESET#/HOOK6 XDP_DBRESET#_R XDP_DBRESET#
47 HOOK3 DBR#/HOOK7 48 1 2 XDP_DBRESET# <13>
49 50 R39 0_0402_5%
SV - i5-450M CPU : 2.4G (K0) 51
GND14 GND15
52 XDP_TDO
PAD T112 SDA TD0
SV - i3-350M CPU : 2.26G (K0) PAD T113 53 54 XDP_TRST#
SCL TRST# XDP_TDI
55 56
SV- i3-370M CPU : 2.4G (K0) Add test points XDP_TCK 57
TCK1 TDI
58 XDP_TMS
TCK0 TMS
ULV -U3400 CPU : 1.06G (K0) 59 GND16 GND17 60
SAMTE_BSH-030-01-L-D-A CONN@ @
XDP_RST#_R 1 2 PLT_RST# PLT_RST# <14,21,22,27>
R42 0_0402_5%
Intel S3 power reduction circuit for Calpella. 11/09
PWM Fan Control circuit
C C
@
PM_PWRBTN#_R 1 2 VDDPWRGOOD_R 1 2 +5VS
+VCCP VCCP_1.5VSPWRGD <29>
R20 1K_0402_5% R12 1.5K_0402_1%
1 2
R13 750_0402_1%
Processor Pullups +3VS
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