Service Manuals, User Guides, Schematic Diagrams or docs for : Compal Compal_LA-6371P
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A B C D E
1 1
Compal Confidential
2 2
Tablet 10" M/B Schematics Document
Intel Pineview-M Processor with DDRIII + Tigerpoint
3 2010-05-07 3
REV:0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/5/7 Deciphered Date 2011/5/7 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-6371P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 1 of 27
A B C D E
A B C D E
Compal Confidential
Memory BUS(DDRIII) Thermal Sensor
Model Name : PAU00 204pin DDRIII-SO-DIMM EMC1402
page 7 page 5
File Name : LA-6371P 1.5V DDRIII 667
1
Intel 1
Pineview-M Clock Generator
PCB CK505
USB port0
ZZZ1 page 8
USB conn x 1
Sub-board
Processor
PCB LCD Conn. LVDS FCBGA559
USB port1
page 9 22x22mm Touch Screen
page 9
page 4,5,6
USB port3
DMI x2 Camera
Sub-board
100MHz USB port7
Mini Card-1
GEN1
page 14
2 2
USB port4
Intel USB 2.0 Mini Card-3 SIM CONN
3.3V 48MHz WWAN
Tigerpoint
NM10 HD Audio Sub-board DMIC
PCI-Express x4 (PCIE1 2.5GT/S) 100MHz
3.3V 24MHz
Audio CKT
port 1 ALC269Q-VB Audio Jack / Speaker
MINI Card -1
WLAN PCBGA 360pins
w/ Bluetooth 17x17mm
page 14
SATA (GEN1 1.5GT/S ,GEN2 3GT/S)
100MHz port 0 SATA SSD
Mini Card-2 page 14
3 3
page 10,11,12,13
LPC BUS
33MHz
Power ON/OFF DC/DC Interface
page 16
page 17
ALS ENE KB926 E0 SPI ROM
3VALW/5VALW page 15 page 15
page 22 page 15
DC IN
page 19
0.89VP/1.8VP
0.75VSP G-Sensor
BATT IN
page 20 page 24 page 15
4 4
CHARGER 1.5V/VCCP
page 21
page 23
CPU_CORE Security Classification Compal Secret Data Compal Electronics, Inc.
page 25 Issued Date 2010/5/7 Deciphered Date 2011/5/7 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-6371P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 2 of 27
A B C D E
A B C D E
Voltage Rails
Power Plane Description S1 S3 S5 External PCI Devices
VIN Adapter power supply (19V) ON ON ON DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. ON ON ON
1
+CPU_CORE Core voltage for CPU ON OFF OFF No PCI Device 1
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+0.89V Graphic core power rail ON OFF OFF
EC SM Bus1 address EC SM Bus2 address
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF Device Address Device Address
+5VALW 5V always on power rail ON ON ON* Smart Battery 0001 011X b EMC1402 100_1100
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Tiger Point SM Bus address
SIGNAL Device Address
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
2 Clock Generator 2
1101 001Xb
Full ON HIGH HIGH HIGH ON ON ON ON (SLG8SP556VTR)
DDR DIMMA 1010 000Xb
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
USB table PCIE table
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
Port0 Ext USB Conn.
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF UHCI1 PCIE port1
Port1 Touch Screen
Port2 PCIE port2 WLAN
EHCI1 UHCI2
Port3 Camera
PCIE port3
Port4 WWAN
UHCI3
Port5 PCIE port4
Port6
UHCI4 PCIE port5
Port7 WLAN
EHCI2 Port8 PCIE port6
UHCI5
Port9
3 3
Port10
UHCI6
Port11
SATA table
SATA port0 SSD
SATA port1
SATA port2
SATA port3
SATA port4
SATA port5
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/5/7 Deciphered Date 2011/5/7 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-6371P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 07, 2010 Sheet 3 of 27
A B C D E
5 4 3 2 1
7 DDR_A_DQS#[0..7] PINEVIEW_M
PINEVIEW_M
U71A
7 DDR_A_D[0..63] U71B
REV = 1.1
REV = 1.1 7 DDR_A_DM[0..7] DDR_A_MA0 DDR_A_DQS0
AH19 DDR_A_MA_0 DDR_A_DQS_0 AD3
C435 1 2 0.1U_0402_16V7K DMI_RX0_C F3 G2 DDR_A_MA1 AJ18 AD2 DDR_A_DQS#0
11 DMI_RX0 DMI_RXP_0 DMI_TXP_0 DMI_TX0 11 7 DDR_A_DQS[0..7] DDR_A_MA_1 DDR_A_DQS#_0
C436 1 2 0.1U_0402_16V7K DMI_RX#0_C F2 G1 DDR_A_MA2 AK18 AD4 DDR_A_DM0
11 DMI_RX#0 DMI_RXN_0 DMI_TXN_0 DMI_TX#0 11 DDR_A_MA_2 DDR_A_DM_0
11 DMI_RX1 C437 1 2 0.1U_0402_16V7K DMI_RX1_C H4 H3 DDR_A_MA3 AK16
DMI_RX#1_C DMI_RXP_1 DMI_TXP_1 DMI_TX1 11 7 DDR_A_MA[0..14] DDR_A_MA4 DDR_A_MA_3 DDR_A_D0
11 DMI_RX#1 C438 1 2 0.1U_0402_16V7K G3 J2 AJ14 AC4
DMI_RXN_1 DMI_TXN_1 DMI_TX#1 11 DDR_A_MA5 DDR_A_MA_4 DDR_A_DQ_0 DDR_A_D1
AH14 AC1
DMI
DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 AF4
Close to CPU DDR_A_MA7 DDR_A_MA_6 DDR_A_DQ_2 DDR_A_D3
AJ12 AG2
Must be placed within 500 mils from Pineview-M pins DDR_A_MA8 DDR_A_MA_7 DDR_A_DQ_3 DDR_A_D4
AH13 AB2
D DDR_A_MA9 DDR_A_MA_8 DDR_A_DQ_4 DDR_A_D5 D
AK12 AB3
EXP_RCOMPO DDR_A_MA10 DDR_A_MA_9 DDR_A_DQ_5 DDR_A_D6
8 CLK_CPU_EXP# N7 L10 AK20 AE2
EXP_CLKINN EXP_RCOMPO R162 49.9_0402_1% DDR_A_MA11 DDR_A_MA_10 DDR_A_DQ_6 DDR_A_D7
8 CLK_CPU_EXP N6 L9 AH12 AE3
EXP_CLKINP EXP_ICOMPI EXP_RBIAS R203 750_0402_1% DDR_A_MA12 DDR_A_MA_11 DDR_A_DQ_7
L8 AJ11
EXP_RBIAS DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 AJ24 AB8
EXP_TCLKINN DDR_A_MA14 DDR_A_MA_13 DDR_A_DQS_1 DDR_A_DQS#1
R9 N11 T38 AJ10 AD7
EXP_TCLKINP RSVD_TP DDR_A_MA_14 DDR_A_DQS#_1 DDR_A_DM1
N10 P11 T39 AA9
RSVD RSVD_TP DDR_A_DM_1
N9
RSVD DDR_A_WE# DDR_A_D8
7 DDR_A_WE# AK22 AB6
DDR_A_CAS# DDR_A_WE# DDR_A_DQ_8 DDR_A_D9
7 DDR_A_CAS# AJ22 AB7
DDR_A_RAS# DDR_A_CAS# DDR_A_DQ_9 DDR_A_D10
7 DDR_A_RAS# AK21 AE5
DDR_A_RAS# DDR_A_DQ_10 DDR_A_D11
K2 K3 AG5
RSVD RSVD DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
J1 RSVD RSVD L2 7 DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M4 M2 DDR_A_BS1 AH20 AB5 DDR_A_D13
RSVD RSVD 7 DDR_A_BS1 DDR_A_BS2 DDR_A_BS_1 DDR_A_DQ_13 DDR_A_D14
L3 RSVD RSVD N2 7 DDR_A_BS2 AK11 DDR_A_BS_2 DDR_A_DQ_14 AB9
AD6 DDR_A_D15
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 DDR_A_DQS_2 AD8
DDR_CS#0 AH22 AD10 DDR_A_DQS#2
7 DDR_CS#0 DDR_CS#1 DDR_A_CS#_0 DDR_A_DQS#_2 DDR_A_DM2
7 DDR_CS#1 AK25 AE8
JP16 DDR_A_CS#_1 DDR_A_DM_2
AJ21 DDR_A_CS#_2
5 XDP_PREQ# XDP_PREQ# 1 CONN@ AJ25 AG8 DDR_A_D16
XDP_PRDY# 1 DDR_A_CS#_3 DDR_A_DQ_16 DDR_A_D17
5 XDP_PRDY# 2 2 DDR_A_DQ_17 AG7
3 DDR_CKE0 AH10 AF10 DDR_A_D18
XDP_BPM#3 3 7 DDR_CKE0 DDR_CKE1 DDR_A_CKE_0 DDR_A_DQ_18 DDR_A_D19
5 XDP_BPM#3 4 4 7 DDR_CKE1 AH9 DDR_A_CKE_1 DDR_A_DQ_19 AG11
5 XDP_BPM#2 XDP_BPM#2 5 AK10 AF7 DDR_A_D20
5 DDR_A_CKE_2 DDR_A_DQ_20 DDR_A_D21
6 6 AJ8 DDR_A_CKE_3 DDR_A_DQ_21 AF8
5 XDP_BPM#1 XDP_BPM#1 7 AD11 DDR_A_D22
XDP_BPM#0 7 M_ODT0 DDR_A_DQ_22 DDR_A_D23
5 XDP_BPM#0 8 7 M_ODT0 AK24 AE10
8 M_ODT1 DDR_A_ODT_0 DDR_A_DQ_23
9 7 M_ODT1 AH26
R354 1 9 DDR_A_ODT_1 DDR_A_DQS3
5,12 H_PWRGD 2 1K_0402_5% 10
10
AH24
DDR_A_ODT_2 DDR_A_DQS_3
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