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A B C D E
1 1
Compal Confidential
2 2
Cougar 2.0
Schematics Document
Intel Cedar Trail Processor/ Tiger point
3 2011-11-07 3
LA-6858P REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBU00
Date: Monday, November 07, 2011 Sheet 1 of 38
A B C D E
A B C D E
Compal Confidential
Model Name : Cougar 2.0
Project Code : QBU00
1
Fan Control Low Power Clock Generator 1
page 26
RTM890N-397
page 9
CRT Conn. RGB
page 15
Intel Cedarview 2 Core 204pin DDRIII-SO-DIMM
HDMI Conn. HDMI Memory BUS(DDRIII)
page 16 1.86GHz (6.5W) page 10
1.5V DDRIII 1066MHz
LED Conn. LVDS (22x22mm) page 6,7,8
page 17 ONE CHANNEL
2
DMI x 2 2
PCIeMini Card
WWAN PCIe port 3 USB Conn X3 Int. Camera
(FULL)
USB port 5 USB USB USB port 0,1,4 USB port 7
page 18
5V 480MHz 5V 480MHz page 19 page 17
PCIeMini Card
PCIe 1x [2]
WLAN +BT COMBO (HALF) 1.5V 2.5GHz(250MB/s)
Tiger Pointer
PCIe port 2 USB port 6 USB Card Reader Card Reader Conn.
page 18
5V 480MHz RTL5137 page 24
USB port 3 page 24
PCIe 1x
(17x17mm)
RJ45 RTL8105E 1.5V 2.5GHz(250MB/s) SATA port 0 SATA HDD
page 23
10/100 LAN 5V 1.5GHz(150MB/s)
page 20
PCIe port 1 page 23
page 11,12,13,14
3 3
RTC CKT.
page 13 SPI ROM 3.3V 24.576MHz/48Mhz
HD Audio
2MB page 26
3.3V 33 MHz
LPC BUS
DC/DC Interface CKT. HDA Codec
ALC269
page 28 page 21
ENE KB930 E0
page 25
Power Circuit DC/DC
Int.
page 29~35 MIC CONN MIC CONN HP CONN SPK CONN
page 21 page 22 page 22 page 22
Touch Pad Int.KBD SPI ROM 128KB (10A 1X) (10B 2X)
page 27 page 27 page 26
4
Power/B 4
page 27
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBU00
Date: W ednesday, June 29, 2011 Sheet 2 of 38
A B C D E
A B C D E
Voltage Rails
1 SIGNAL 1
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 G3
Full ON HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) ON ON ON OFF
B+ AC or battery power rail for power circuit. ON ON ON ON S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+GFX_CORE GFX support voltage ON OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+1.05VS VCCP switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.5V 1.5V power rail for DDR ON ON OFF OFF
+1.8VS 1.8VS switched power rail ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON ON OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
+3V_WLAN 3.3V power rail for LAN ON OFF OFF OFF BTO Option Table
2 2
+3VS 3.3V switched power rail ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON OFF Function Mini PCI-E SLOT Display Clock gen
+5VS 5V switched power rail ON OFF OFF OFF
+VSB VSB always on power rail ON ON ON OFF
description
+RTCVCC RTC power ON ON ON ON explain Wi-Fi WWAN 3G CRT HDMI Tpye
+3VS_PRIME 3.3V power rail for CPU and PCH ON OFF OFF OFF
BTO WLAN@ WWAN@ 3G@ CRT@ HDMI@ low@ normal@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3 3
EC SM Bus1 address EC SM Bus2 address
Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 010X b
NM10 SM Bus address
Device Address
Clock Generator 1101 001Xb
(SLG8SP556VTR)
DDR DIMMA 1010 000Xb
WWAN/WLAN
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBU00
Date: W ednesday, June 29, 2011 Sheet 3 of 38
A B C D E
5 4 3 2 1
D D
C C
B B
A
Security Classification Compal Secret Data Compal Electronics, Inc. A
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBU00
Date: Wednesday, June 29, 2011 Sheet 4 of 38
5 4 3 2 1
5 4 3 2 1
B+ DESIGN CURRENT 250mA Cougar Power Map
Ipeak=6.97A, Imax=4.88A
DESIGN CURRENT 522mA
+3VALWP +-5%
** The SW just is reserved.
The power passes by jump or
TPS51125ARGER 0-ohm resistor. WOL_EN#
** P-CHANNEL +3V_LAN
AO3413 DESIGN CURRENT 300mA
D D
Ipeak=3.98A, Imax=2.8A +5VALWP +-5%
DESIGN CURRENT 3010mA
SUSP
N-CHANNEL +5VS
DESIGN CURRENT 2286mA
SI7326DN
VGATE
APL5930KA DESIGN CURRENT 151mA
+1.8VS
C C
SUSP
N-CHANNEL DESIGN CURRENT 5586mA
+3VS
SI7326DN ENVDD
P-CHANNEL +LCD_VDD
AO3413 DESIGN CURRENT 2000mA
VGATE#
N-CHANNEL DESIGN CURRENT 294mA
+3VS_PRIME
SUSP# SI7326DN
SY8033BDBC Ipeak=1.308A, Imax=4A +1.05VSP +-5%
DESIGN CURRENT 3489mA
VR_ON
B Imax=3.5A DESIGN CURRENT 4500mA +CPU_COREP B
RT8165BGQW DESIGN CURRENT 2000mA +GFX_COREP
SYSON
Ipeak=19.6A, Imax=13.72A +1.5VP +-5%
DESIGN CURRENT 2270mA
G5603RU1U
SUSP#
DESIGN CURRENT 2112mA +1.5VSP
SI7326DN
SUSP
DESIGN CURRENT 500mA
+0.75VSP
G2992F1U
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power tree
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBU00
Date: Wednesday, June 29, 2011 Sheet 5 of 38
5 4 3 2 1
5 4 3 2 1
N2800@
<10> DDR_A_MA[0..15] U1
QB0Y B2 1.86G
<10> DDR_A_DQS#[0..7]
<10> DDR_A_DM[0..7]
<10> DDR_A_DQS[0..7] N2600@
U1B
U1A N2600@ ?
CEDARVIEW
<10> DDR_A_D[0..63] DDR_A_MA0 AK14 DDR_A_D0
CEDARVIEW
DDR3_MA0 DDR3_DQ0 Y30
DDR_A_MA1 AK16 Y29 DDR_A_D1
REV = 1.10 DDR_A_MA2 AJ14 DDR3_MA1 REV = 1.10 DDR3_DQ1 DDR_A_D2
DDR3_MA2 DDR3_DQ2 AC30
DMI_RXP0_C L3 K6 DMI_TXP0 <12> DDR_A_MA3 AJ16 AC31 DDR_A_D3
DMI_RXN0_C DMI_RXP0 DMI_TXP0 DDR_A_MA4 AK18 DDR3_MA3 DDR3_DQ3 DDR_A_D4
L2 DMI_RXN0 DMI_TXN0 K5 DMI_TXN0 <12> DDR3_MA4 DDR3_DQ4 W31
D DMI_RXP1_C DDR_A_MA5 AH18 DDR_A_D5 D
M3 DMI_RXP1 DMI_TXP1 L5 DMI_TXP1 <12> DDR3_MA5 DDR3_DQ5 W28
DMI_RXN1_C M2 L6 DDR_A_MA6 AJ18 AB28 DDR_A_D6
DMI_RXN1 DMI_TXN1 DMI_TXN1 <12> DDR3_MA6 DDR3_DQ6
N2 L9 DDR_A_MA7 AK20 AB30 DDR_A_D7
DMI_RXP2 DMI_TXP2 DDR_A_MA8 AJ20 DDR3_MA7 DDR3_DQ7 DDR_A_D8
N1 L8 AA24
DMI_RXN2 DMI_TXN2 DDR_A_MA9 AH20 DDR3_MA8 DDR3_DQ8 DDR_A_D9
P2 N5 AA22
DMI
DMI_RXP3 DMI_TXP3 DDR_A_MA10 AJ12 DDR3_MA9 DDR3_DQ9 DDR_A_D10
P3 DMI_RXN3 DMI_TXN3 N6 DDR3_MA10 DDR3_DQ10 AE27
+1.5VS DDR_A_MA11 AK21 AE26 DDR_A_D11
DDR_A_MA12 AJ21 DDR3_MA11 DDR3_DQ11 DDR_A_D12
<9> CLK_CPU_EXP N9 DMI_REFCLKP RSVD_TP_R8 R8 T1 R493 DDR3_MA12 DDR3_DQ12 AB27
N8 R7 DDR_A_MA13 AJ8 AA25 DDR_A_D13
<9> CLK_CPU_EXP# DMI_REFCLKN RSVD_TP_R7 T2 DDR3_MA13 DDR3_DQ13
2 1 DMI_REF1P5 T2 T1 DMI_IRCOMP1 2 DMI_REF1P5 DDR_A_MA14 AH22 AD25 DDR_A_D14
DMI_REF1P5 DMI_RCOMP DDR3_MA14 DDR3_DQ14
1U_0402_6.3V6K
R973 0_0402_5% DDR_A_MA15 AJ22 AD27 DDR_A_D15
7.5K_0402_5% DDR3_MA15 DDR3_DQ15 DDR_A_D16
1 AD29
DDR3_DQ16
C1088
+1.5V pull up must be placed DDR_A_WE# AH10 AE29 DDR_A_D17
<10> DDR_A_WE# DDR3_WE# DDR3_DQ17
1 OF 6 DDR_A_CAS# AJ10 AJ30 DDR_A_D18
within 500 mils from Cedarview <10> DDR_A_CAS# DDR_A_RAS# AJ11
DDR3_CAS# DDR3_DQ18
AK29 DDR_A_D19
2 QB0Z B2 1.6G <10> DDR_A_RAS# DDR3_RAS# DDR3_DQ19
? AD28 DDR_A_D20
DDR_A_BS0 DDR3_DQ20 DDR_A_D21
<10> DDR_A_BS0 AK12 DDR3_BS0 DDR3_DQ21 AD30
DDR_A_BS1 AH13 AG30 DDR_A_D22
<10> DDR_A_BS1 DDR3_BS1 DDR3_DQ22
+1.5V pull up must be placed DDR_A_BS2 AK22 AJ29 DDR_A_D23
<10> DDR_A_BS2 DDR3_BS2 DDR3_DQ23 DDR_A_D24
AE24
within 500 mils from Cedarview AH12
DDR3_DQ24
AG24 DDR_A_D25
DDR3_CS#0 DDR3_DQ25 DDR_A_D26
AH8 AD22
DDR_CS2# DDR3_CS#1 DDR3_DQ26 DDR_A_D27
<10> DDR_CS2# AK11 DDR3_CS#2 DDR3_DQ27 AC21
DDR_CS3# AK8 AG27 DDR_A_D28
<10> DDR_CS3# DDR3_CS#3 DDR3_DQ28 DDR_A_D29
AG25
C948 1 DMI_RXP0_C DDR3_DQ29 DDR_A_D30
<12> DMI_RXP0 2 AH23 DDR3_CKE0 DDR3_DQ30 AG21
0.1U_0402_10V6K AJ24 AE21 DDR_A_D31
DDR_CKE2 DDR3_CKE1 DDR3_DQ31 DDR_A_D32
<10> DDR_CKE2 AK24 AD13
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