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A B C D E
w w w . b u f a n x i u . c o m
1 1
Compal Confidential
2 2
Schematics Document
Intel Huron River
Sandy Bridge with Couger Point core logic
3
2010-10-27 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/25 Deciphered Date 2010/08/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6931P
Date: Wednesday, October 27, 2010 Sheet 1 of 58
A B C D E
A B C D E
Compal Confidential w w w . b u f a n x i u . c o m
Model Name : P5LM0
File Name : LA-6931P Fan Control
page 43
1 1
100MHz PCI-E 2.0x16 5GT/s PER LANE
ATI PEG(DIS) Intel Memory BUS(DDRIII)
Granville-Pro/Whistler-Pro 133MHz Dual Channel 204pin DDRIII-SO-DIMM X4
Sandy Bridge (DIS) BANK 0, 1, 2, 3 page 10,11
page 1.5V DDRIII: 1066MT/S
22,23,24,25,26,27,28 Processor 1333MT/S
rPGA989
LVDS(DIS) 37.5mm*37.5mm
CRT(DIS) LVDS Conn. page 4,5,6,7,8,9,10
page 29
HDMI(DIS) USB conn x2 Bluetooth CMOS Camera TV Tuner
FDI x8 DMI x4 USB port 0,1
(UMA) USB Port 2 (eSATA)
Conn
USB port 3
HDMI Conn. CRT CRT Conn. LVDS 100MHz 100MHz
USB port 10 USB port 5
page 29 page 35 page 42 page 29 page 38
page 30 page 30 2.7GT/s 1GB/s x4
page 31 3.3V 48MHz
2
LVDS(UMA) USBx14 2
CRT(UMA)
Cougar Point-M
HD Audio 3.3V 24MHz
PCH
989pins SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz
PCI-Express x 8 (PCIE1/2 2.5/5GT/S) 100MHz 25mm*25mm
HDA Codec
page 13,14,15,16,17 ALC669X
port 5 port 4 port 2 port 1
18,19,20,21 SPI page 41
CardReader USB3.0 conn x 1 MINI Card x1 LAN(GbE) port 0 port 1 port 4
R5U232 NEC UPD720200F1 WLAN RTL8111E SATA HDD SATA ODD eSATA
SPI ROM x1 Audio AMP
page 37 page 36 page 38 page 33 Conn. Conn. Conn.
page 13 page 32 page 32 page 35
TPA6017
page 42
3
RJ45 LPC BUS 3
page 33
33MHz Phone Jack x 3
Int. Speaker
+SubWoofer
ENE KB930 page 42 page 42
Sub-board
page 39
LS-6931P
RTC CKT. Power/B
page 41
page 13
Touch Pad Int.KBD
LS-6932P page 34 page 40
ARCADE/B
Power On/Off CKT. page29
page 40 EC I/O Buffer BIOS ROM
LS-6933P page 39 page 40
FP/B
page 44
DC/DC Interface CKT.
4
page 44,45 LS-6934P 4
USB/B
page 43
Power Circuit DC/DC LS-6935P
TP/B
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/25 Deciphered Date 2010/08/25 Title
page 46~55 page 35 Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6931P
Date: Wednesday, October 27, 2010 Sheet 2 of 58
A B C D E
A B C D E
Voltage Rails SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 w w IGPU
S5w DGPU . b u f a nxiu.com
(DIS) (SG) Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
BATT+ Battery power supply (12.6V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
+1.05VS_VCCP 1.05V switched power rail for CPU (PCH) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGFX_CORE Core voltage for IGPU ON OFF OFF
+1.5V 1.5V power rail for DDRIII ON ON OFF
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Ra/Rc/Re 100K +/- 5%
+3VALW_PCH 3.3V power rail for PCH ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+LAN_IO 3.3V power rail for LAN ON ON ON* 0 0 0 V 0 V 0 V
+3VS 3.3V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VALW 5V always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VS 5V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+VSB VSB always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+RTCVCC RTC power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+VGA_CORE 5V power rail for GPU ON OFF OFF ON OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+1.5VSDGPU 1.5V power rail for VRAM ON OFF OFF ON OFF 7 NC 2.500 V 3.300 V 3.300 V
2 2
+1.8VSDGPU 1.8V switched power rail for GPU ON OFF OFF ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. BOARD ID Table BTO Option Table
BTO Item BOM Structure
Board ID PCB Revision
External PCI Devices DIS Only DIS@
0 0.1
Switchable
Device IDSEL# REQ#/GNT# Interrupts 1 SG@
Graphics
2
Granville GRA@
* 3 0.4
Whistler WHI@
4
For CIR CIR@
5
USB2.0 bus USB2@
6
DDR M1 M1@
EC SM Bus1 address EC SM Bus2 address 7
DDR M3 M3@
For 45 level 45@
Device Address Device Address
USB Port Table
4 External
3 USB 2.0 USB 1.1 Port USB Port 3
0 USB/B
UHCI0
Ibex SM Bus address 1 USB Conn.
2
Device Address UHCI1
3
EHCI1 43 Level BOM Config
4 Mini Card 1
UHCI2
5 Mini Card 2 Granville DIS: GRA@ DIS@ CIR@ M1@
6 Whistler SG: WHI@ SG@ CIR@ M1@
UHCI3 45 Level BOM Config
7
45@
8 USB Conn.
UHCI4 VRAM BOM Config
9 eSATA USB
10 CMOS Camera
EHCI2 UHCI5 X76255BOL01: HYNIX 1G (old die)
11 Finger Print
X76255BOL02 HYNIX 1G (new die)
12 USB3.0 @
4 UHCI6 X76255BOL04 HYNIX 2G 4
13 Blue Tooth
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/25 Deciphered Date 2010/08/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6931P
Date: Wednesday, October 27, 2010 Sheet 3 of 58
A B C D E
5 4 3 2 1
www.bufanxiu.com
D D
+1.05VS_VCCP
1
R1
24.9_0402_1%
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
<15> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
<15> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<15> DMI_CRX_PTX_N2 A25 DMI_RX#[2]
<15> DMI_CRX_PTX_N3 B24 K33 PEG_HRX_GTX_N15
DMI_RX#[3] PEG_RX#[0] PEG_HRX_GTX_N14
PEG_RX#[1] M35
B28 L34 PEG_HRX_GTX_N13
<15> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2] PEG_HRX_GTX_N[0..15] <22>
B26 J35 PEG_HRX_GTX_N12
<15> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3] PEG_HRX_GTX_P[0..15] <22>
DMI
<15> DMI_CRX_PTX_P2 A24 J32 PEG_HRX_GTX_N11
DMI_RX[2] PEG_RX#[4] PEG_HRX_GTX_N10
<15> DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34 PEG_HTX_C_GRX_N[0..15] <22>
H31 PEG_HRX_GTX_N9
PEG_RX#[6] PEG_HRX_GTX_N8 PEG_HTX_C_GRX_P[0..15] <22>
<15> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PEG_HRX_GTX_N7
<15> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PEG_HRX_GTX_N6
<15> DMI_CTX_PRX_N2 F21 DMI_TX#[2] PEG_RX#[9] F35
D21 E34 PEG_HRX_GTX_N5
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_HRX_GTX_N4
PEG_RX#[11] PEG_HRX_GTX_N3
<15> DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33
D22 D31 PEG_HRX_GTX_N2
<15> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PEG_HRX_GTX_N1
PCI EXPRESS* - GRAPHICS
<15> DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33
C21 C32 PEG_HRX_GTX_N0
<15> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PEG_HRX_GTX_P15
C PEG_RX[0] PEG_HRX_GTX_P14 C
PEG_RX[1] L35
K34 PEG_HRX_GTX_P13
PEG_RX[2] PEG_HRX_GTX_P12
<15> FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PEG_HRX_GTX_P11
<15> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] PEG_HRX_GTX_P10
<15> FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34
F18 G31 PEG_HRX_GTX_P9
Intel(R) FDI
<15> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] PEG_HRX_GTX_P8
<15> FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33
C20 F30 PEG_HRX_GTX_P7
<15> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] PEG_HRX_GTX_P6
<15> FDI_CTX_PRX_N6 D18 E35
FDI1_TX#[2] PEG_RX[9] PEG_HRX_GTX_P5
<15> FDI_CTX_PRX_N7 E17 E33
FDI1_TX#[3] PEG_RX[10] PEG_HRX_GTX_P4
F32
PEG_RX[11] PEG_HRX_GTX_P3
D34
PEG_RX[12] PEG_HRX_GTX_P2
<15> FDI_CTX_PRX_P0 A22 E31
FDI0_TX[0] PEG_RX[13] PEG_HRX_GTX_P1
<15> FDI_CTX_PRX_P1 G19 C33
FDI0_TX[1] PEG_RX[14] PEG_HRX_GTX_P0
<15> FDI_CTX_PRX_P2 E20 B32
FDI0_TX[2] PEG_RX[15]
<15> FDI_CTX_PRX_P3 G18
FDI0_TX[3] PEG_HTX_GRX_N15 C1 0.22U_0402_10V6K PEG_HTX_C_GRX_N15
<15> FDI_CTX_PRX_P4 B20 M29 1 2
FDI1_TX[0] PEG_TX#[0] PEG_HTX_GRX_N14 C2 0.22U_0402_10V6K PEG_HTX_C_GRX_N14
<15> FDI_CTX_PRX_P5 C19 M32 1 2
FDI1_TX[1] PEG_TX#[1] PEG_HTX_GRX_N13 C3 0.22U_0402_10V6K PEG_HTX_C_GRX_N13
<15> FDI_CTX_PRX_P6 D19 M31 1 2
FDI1_TX[2] PEG_TX#[2] PEG_HTX_GRX_N12 C4 0.22U_0402_10V6K PEG_HTX_C_GRX_N12
<15> FDI_CTX_PRX_P7 F17 L32 1 2
FDI1_TX[3] PEG_TX#[3] PEG_HTX_GRX_N11 C5 0.22U_0402_10V6K PEG_HTX_C_GRX_N11
L29 1 2
+1.05VS_VCCP PEG_TX#[4] PEG_HTX_GRX_N10 C6 0.22U_0402_10V6K PEG_HTX_C_GRX_N10
<15> FDI_FSYNC0 J18 K31 1 2
FDI0_FSYNC PEG_TX#[5] PEG_HTX_GRX_N9 C7 0.22U_0402_10V6K PEG_HTX_C_GRX_N9
<15> FDI_FSYNC1 J17 K28 1 2
FDI1_FSYNC PEG_TX#[6] PEG_HTX_GRX_N8 C8 0.22U_0402_10V6K PEG_HTX_C_GRX_N8
J30 1 2
PEG_TX#[7] PEG_HTX_GRX_N7 C9 0.22U_0402_10V6K PEG_HTX_C_GRX_N7
<15> FDI_INT H20 J28 1 2
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 C10 0.22U_0402_10V6K PEG_HTX_C_GRX_N6
H29 1 2
PEG_TX#[9]
1
J19 G27 PEG_HTX_GRX_N5 C11 1 2 0.22U_0402_10V6K PEG_HTX_C_GRX_N5
<15> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
R296 <15> FDI_LSYNC1 H17 E29 PEG_HTX_GRX_N4 C12 1 2 0.22U_0402_10V6K PEG_HTX_C_GRX_N4
FDI1_LSYNC PEG_TX#[11] PEG_HTX_GRX_N3 C13 0.22U_0402_10V6K PEG_HTX_C_GRX_N3
24.9_0402_1% F27 1 2
PEG_TX#[12] PEG_HTX_GRX_N2 C14 0.22U_0402_10V6K PEG_HTX_C_GRX_N2
D28 1 2
PEG_TX#[13] PEG_HTX_GRX_N1 C15 0.22U_0402_10V6K PEG_HTX_C_GRX_N1
F26 1 2
2
PEG_TX#[14] PEG_HTX_GRX_N0 C16 0.22U_0402_10V6K PEG_HTX_C_GRX_N0
E25 1 2
B EDP_COMP PEG_TX#[15] B
A18
eDP_COMPIO PEG_HTX_GRX_P15 C17 0.22U_0402_10V6K PEG_HTX_C_GRX_P15
A17 M28 1 2
eDP_ICOMPO PEG_TX[0] PEG_HTX_GRX_P14 C18 0.22U_0402_10V6K PEG_HTX_C_GRX_P14
B16 M33 1 2
eDP_HPD PEG_TX[1] PEG_HTX_GRX_P13 C19 0.22U_0402_10V6K PEG_HTX_C_GRX_P13
M30 1 2
PEG_TX[2] PEG_HTX_GRX_P12 C20 0.22U_0402_10V6K PEG_HTX_C_GRX_P12
L31 1 2
PEG_TX[3] PEG_HTX_GRX_P11 C21 0.22U_0402_10V6K PEG_HTX_C_GRX_P11
C15 L28 1 2
eDP_AUX PEG_TX[4] PEG_HTX_GRX_P10 C22 0.22U_0402_10V6K PEG_HTX_C_GRX_P10
D15 K30 1 2
eDP_AUX# PEG_TX[5]
eDP
eDP_COMPIO and ICOMPO signals K27 PEG_HTX_GRX_P9 C23 1 2 0.22U_0402_10V6K PEG_HTX_C_GRX_P9
PEG_TX[6] PEG_HTX_GRX_P8 C24 0.22U_0402_10V6K PEG_HTX_C_GRX_P8
J29 1 2
should be shorted near balls C17
PEG_TX[7]
J27 PEG_HTX_GRX_P7 C25 1 2 0.22U_0402_10V6K PEG_HTX_C_GRX_P7
eDP_TX[0] PEG_TX[8]
and routed with typical F16
eDP_TX[1] PEG_TX[9]
H28 PEG_HTX_GRX_P6 C26 1 2 0.22U_0402_10V6K PEG_HTX_C_GRX_P6
C16 G28 PEG_HTX_GRX_P5 C27 1 2 0.22U_0402_10V6K PEG_HTX_C_GRX_P5
impedance <25 mohms G15
eDP_TX[2] PEG_TX[10]
E28 PEG_HTX_GRX_P4 C28 1 2 0.22U_0402_10V6K PEG_HTX_C_GRX_P4
eDP_TX[3] PEG_TX[11] PEG_HTX_GRX_P3 C29 0.22U_0402_10V6K PEG_HTX_C_GRX_P3
F28 1 2
PEG_TX[12] PEG_HTX_GRX_P2 C30 0.22U_0402_10V6K PEG_HTX_C_GRX_P2
C18 D27 1 2
eDP_TX#[0] PEG_TX[13] PEG_HTX_GRX_P1 C31 0.22U_0402_10V6K PEG_HTX_C_GRX_P1
E16 E26 1 2
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