Service Manuals, User Guides, Schematic Diagrams or docs for : Compal Compal_LA-7291P
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A B C D E
1 1
PEQAE
2
Erie 10AS/10ASG 2
LA-7291P REV 1.0 Schematic
3
AMD Llano FS1 Processor / Hudson M2/M3 3
Whistler LP & Whistler Pro
2011-04-26 Rev 1.0
Toshiba Satellite P7xx P755
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/11 Deciphered Date 2011/11/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A7291
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019CQ
Date: Thursday, May 05, 2011 Sheet 1 of 52
A B C D E
A B C D E
EC SMBus HDMI-CEC PWM Fan Control
page 5
page 30 PCI-Express X4 5GHz AMD APU
HDMI Conn.
VGA HDMI
FS1 Processor
page 30
Memory BUS(DDRIII)
1 200pin DDRIII-SO-DIMM X2 1
PCI-Express X16 5GHz Llano uPGA-722 Dual Channel page 10,11
35mm*35mm
BANK 0, 1, 2, 3
VGA Thermal Sensor
1.5V DDRIII 1066/1333 MT/s
ADM1032ARMZ-2 page 5,6,7,8,9
page 13
DP0 DP1
LVDS Translator (X1) (X4) PCIe X1 X1 USB/B Right Left USB FingerPrinter
UMI X4 1.1V 5GT/s
AMD GPU ANX3110 2.5GT/s USB port 0,1 USB port 2 USB port 7
page 31 page 31 page 32
page 27
AMD Capilano LP, 128bit with 1GB/2GB DDR3 PCIe X1
AMD Whistler LP, 128bit with 1GB/2GB DDR3 1.1V 5GT/s USB 3.0 Felica Int. Camera
VGA LVDS
USB port 10 USB port 9 USB port 5
FCBGA-962 LVDS Conn. USB page 36 page 32 page 28
29mm*29mm VGA eDP 5V 480MHz
page 13,14,15,16,17,18,19,20,21 page 28
PCIeMini Card PCIeMini Card SIM
2
USB WLAN 3G USB port 6
page 39 2
IR Emitter 5V 480MHz page 33
page 32
VGA CRT CRT
USB port 8 PCIeMini Card
page 29 page 33
APU PCIe port 1
JET APU PCIe port 2
AMD FCH page 33 page 33
RTL8105E 10/100M Hudson M2/M3
RJ45 SATA port 0 SATA HDD
page 34
RTL8111E 1G 5V 6GHz(600MB/s) SATA port 0
APU PCIe port 0 page 31
page 34
FCBGA-656 SATA port 1 SATA ODD
24.5mm*24.5mm
5V 6GHz(600MB/s) SATA port 1
page 31
Cardreader PCIe X1
JMB389C 1.1V 5GT/s
USB 3.0 port0 USB 3.0
FCH PCIe port2 page 22,23,24,25,26 5GHz USB3.0 port0
page 35 page 36
3
PCIe X1 USB3.0 3
SPI Bus 1.1V 5GT/s UPD720200AF1-DAP-A
3.3V 33 MHz FCH PCIe port1
page 36
LPC Bus HD Audio 3.3V 24MHz
3.3V 33 MHz
TP& Light Pipe/B
LS-6061P page 40 HDA Codec
ALC269
Cap Sensor SPI ROM Debug Port ENE KB930 page 37
page 39 page 38
& Light Sensor/B (2MB) 24
page
RTC CKT. LS-6062P page 40
page 22
Touch Pad Int.KBD EC ROM CIR G-Sensor Int. SPK Conn JPIO
page 37
LED/B page 40 page 39 page 38 page 39 MIC Conn (HP & MIC)
DC/DC Interface CKT. LS-6063P page 40
(128KB) 39
page
page 28 page 31
page 41 EC SMBus
Audio & USB/B
4 4
Power Circuit DC/DC LS-6064P page 31
page 42,43,44,45,46
47,48,49,50
Finger Printer/B
LS-6065P page 32 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/11 Deciphered Date 2011/11/11 Title
Power On/Off CKT. Power/B_FPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A7291
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
page 40 DA300006JM0 page 40 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019CQ B
Date: Thursday, May 05, 2011 Sheet 2 of 52
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL
DESIGN CURRENT 0.1A +5VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9A DESIGN CURRENT 5A +5VALW
SUSP
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
KB_LED
DESIGN CURRENT 400mA +5VS_LED
P-CHANNEL
D AO-3413 D
+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191
ODD_PWR
TPS51125A DESIGN CURRENT 1.6A
P-CHANNEL
+5VS_ODD
AO-3413
Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SYSON
DESIGN CURRENT 0.2A +3V
P-CHANNEL
AO-3413
GPU_PWREN
DESIGN CURRENT 1.65A +1.8VSG
SY8033BDBC
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800 LCD_ENVDD
C C
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
FELICA_PWR
DESIGN CURRENT 0.5A +FLICA_VCC
P-CHANNEL
AO-3413
PXS_PWREN
DESIGN CURRENT 0.3A +3VSG
P-CHANNEL
AO-3413
+3VS
LDO DESIGN CURRENT 1A +2.5VS
APL5508-25DC
POK
Ipeak=5.3A, Imax=3.71A, Iocp min=6.814A DESIGN CURRENT 5.3A +1.1VALW
G5603RU1U
SUSP
N-CHANNEL DESIGN CURRENT 4A +1.1VS
FDS6676AS
VR_ON
Ipeak=54A, Imax=36A, Iocp min=65A DESIGN CURRENT 50A +CPU_CORE
ISL6267HRZ-T Ipeak=27.5A, Imax=22A, Iocp min=35A DESIGN CURRENT 23A
B
+CPU_CORE_NB B
VR_ON
Ipeak=6.5A, Imax=4.55A, Iocp min=8.553A DESIGN CURRENT 6.5A +1.2VS
G5603RU1U
SYSON
Ipeak=20A, Imax=11.2A, Iocp min=24.136A DESIGN CURRENT 20A +1.5V
G5603RU1U SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5VS
FDS6676AS
+3V
LDO DESIGN CURRENT 1A +1.05V
APL5930KAI-TRG
SUSP
DESIGN CURRENT 1.5A +0.75VS
G2992F1U
VGA_PWRGD
N-CHANNEL DESIGN CURRENT 11A +1.5VSG
FDS6676AS
A A
GPU_PWREN
LDO DESIGN CURRENT 3A +1.0VSG
APL5930KAI
VGACORE_EN
Ipeak=32.6A, Imax=20.3A, Iocp min=36A DESIGN CURRENT 32.6A +VGA_CORE
RT8237CZQW
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/11 Deciphered Date 2011/11/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A7291
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019CQ
Date: Thursday, May 05, 2011 Sheet 3 of 52
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )
Voltage Rails
+5VS BTO Option Table
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW +3V Function HDMI SKU
+2.5VS
+1.1VALW +1.05V
power +1.5VS description HDMI SKU
1 plane +VSB 1
+1.2VS UMA
explain PowerXpress Discrete COMMON CEC UMA PowerXpress Discrete
+1.1VS
+0.75VS BTO IHDMI@ DHDMI@ HDMI@ CEC@ UMA@ UMA@+VGA@+PXS@ VGA@+DIS@
+CPU_CORE
+CPU_CORE_NB
Function MINI PCI-E SLOT LAN Fingerprint CIR KB Light
+VGA_CORE
State
+3VSG description 3G LAN Fingerprint CIR KB Light
+1.8VSG
explain 3G 10/100M GIGA Fingerprint CIR KB Light
+1.5VSG
+1.0VSG BTO 3G@ 8105ELDO@ 8105ESWR@ 8111E@ FP@ CIR@ KBL@
S0 Function Felica G-SENSOR Cam & Mic Panel
O O O O O O
description Felica G-SENSOR Cam & Mic Panel (DIS@)
S1
O O O O O O
explain Felica G-SENSOR Cam & Mic 3D LVDS eDP Non-3D & EDP
2 2
S3
O O O O O X BTO FELICA@ GSENSOR@ CAM@ 3D@+NOEDP@ EDP@ NO3D@+NOEDP@
S5 S4/AC
O O O O X X
Function GPIO for PowerXpress Chipset
S5 S4/ Battery only
O O O X X X description PowerXpress (PXS@) FCH GPU
S5 S4/AC & Battery explain PowerXpress Enable Crossfire Enable Hudson-M3 Whistler Pro
don't exist
O X X X X X
BTO PXSEN@ CROSSEN@ HUDM3R1@ HUDM3R3@ WHPROR1@ WHPROR3@
Function PowerXpress Renesas USB3.0 FCH EC
description PowerXpress Renesas USB3.0 FCH EC
FCH SM Bus Address (SCL0/SDA0)
explain BACO mode Non-BACO Renesas USB3.0 Hudson-M2 Hudson-M3 KB-930 KB-9012
Power Device HEX Address BACO@ NOBACO@ RENE@ M2@ M3@ KB930@ KB9012@
BTO
3 3
+3VS DDR SO-DIMM 0 A0 H 1010 000X b
+3VS DDR SO-DIMM 1 A2 H 1010 001X b
+3VS WLAN
+3VS 3G
SIGNAL
STATE SLP_S3# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH
Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS CPU Thermal Sensor 98 H 1001 1001 b
S3 (Suspend to RAM) LOW HIGH
+3VL HDMI-CEC 34 H 0011 0100 b +3VS GPU Thermal Sensor 82 H 1000 0010 b
+3VS G-Sensor 40 H 0100 0000 b S4 (Suspend to Disk) LOW HIGH
+3VS Light Sensor 52 H 0101 0010 b
S5 (Soft OFF) LOW LOW
+3VS LVDS EEPROM A8 H 1010 1000 b
4
Power Device HEX Address C0 H
4
+3VS 3D - Bootloader 1100 0000 b G3 LOW LOW
+3VL Cap. Sensor Virtual I2C +3VS 3D - Slave 60 H 0110 0000 b
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/11 Deciphered Date 2011/11/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A7291
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019CQ
Date: Thursday, May 05, 2011 Sheet 4 of 52
A B C D E
A B C D E
<12> PCIE_GTX_C_FRX_P[0..15] PCIE_FTX_C_GRX_P[0..15] <12>
<12> PCIE_GTX_C_FRX_N[0..15] PCIE_FTX_C_GRX_N[0..15] <12>
JAPUA @
PCI EXPRESS
PCIE_GTX_C_FRX_P0 AA8 AA2 PCIE_FTX_GRX_P0 C1 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P0
P_GFX_RXP0 P_GFX_TXP0
PCIE_GTX_C_FRX_N0 AA9 AA3 PCIE_FTX_GRX_N0 C2 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N0
P_GFX_RXN0 P_GFX_TXN0
PCIE_GTX_C_FRX_P1 Y7 Y2 PCIE_FTX_GRX_P1 C3 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P1
P_GFX_RXP1 P_GFX_TXP1
1 PCIE_GTX_C_FRX_N1 PCIE_FTX_GRX_N1 C4 PCIE_FTX_C_GRX_N1 1
Y8 P_GFX_RXN1 P_GFX_TXN1 Y1 1 2 VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_FRX_P2 W5 Y4 PCIE_FTX_GRX_P2 C9 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P2
P_GFX_RXP2 P_GFX_TXP2
PCIE_GTX_C_FRX_N2 W6 Y5 PCIE_FTX_GRX_N2 C22 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N2
P_GFX_RXN2 P_GFX_TXN2
PCIE_GTX_C_FRX_P3 W8 W2 PCIE_FTX_GRX_P3 C23 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P3
P_GFX_RXP3 P_GFX_TXP3
PCIE_GTX_C_FRX_N3 W9 W3 PCIE_FTX_GRX_N3 C24 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N3
P_GFX_RXN3 P_GFX_TXN3
PCIE_GTX_C_FRX_P4 V7 V2 PCIE_FTX_GRX_P4 C25 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P4
For PowerXpress
P_GFX_RXP4 P_GFX_TXP4
PCIE_GTX_C_FRX_N4 V8 V1 PCIE_FTX_GRX_N4 C26 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N4
P_GFX_RXN4 P_GFX_TXN4
PCIE_GTX_C_FRX_P5 U5 V4 PCIE_FTX_GRX_P5 C27 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P5
P_GFX_RXP5 P_GFX_TXP5
PCIE_GTX_C_FRX_N5 U6 V5 PCIE_FTX_GRX_N5 C28 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N5
P_GFX_RXN5 P_GFX_TXN5
PCIE_GTX_C_FRX_P6 U8 U2 PCIE_FTX_GRX_P6 C29 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P6
P_GFX_RXP6 P_GFX_TXP6
GRAPHICS
PCIE_GTX_C_FRX_N6 U9 U3 PCIE_FTX_GRX_N6 C30 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N6
P_GFX_RXN6 P_GFX_TXN6
PCIE_GTX_C_FRX_P7 T7 T2 PCIE_FTX_GRX_P7 C31 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P7
P_GFX_RXP7 P_GFX_TXP7
PCIE_GTX_C_FRX_N7 T8 T1 PCIE_FTX_GRX_N7 C32 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N7
Place R1 ~ R8 close to C33 ~ C40
P_GFX_RXN7 P_GFX_TXN7
PCIE_GTX_C_FRX_P8 R5 T4 PCIE_FTX_GRX_P8 C33 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P8 PCIE_FTX_GRX_P8 R1 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX2+ <30>
P_GFX_RXP8 P_GFX_TXP8
PCIE_GTX_C_FRX_N8 R6 T5 PCIE_FTX_GRX_N8 C34 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N8 PCIE_FTX_GRX_N8 R2 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX2- <30>
P_GFX_RXN8 P_GFX_TXN8
PCIE_GTX_C_FRX_P9 R8 R2 PCIE_FTX_GRX_P9 C35 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P9 PCIE_FTX_GRX_P9 R3 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX1+ <30>
P_GFX_RXP9 P_GFX_TXP9
2 PCIE_GTX_C_FRX_N9 PCIE_FTX_GRX_N9 C36 PCIE_FTX_C_GRX_N9 PCIE_FTX_GRX_N9 2
R9 P_GFX_RXN9 P_GFX_TXN9 R3 1 2 DIS@ 0.1U_0402_16V7K R4 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX1- <30>
PCIE_GTX_C_FRX_P10 P7 P2 PCIE_FTX_GRX_P10 C37 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P10 PCIE_FTX_GRX_P10 R5 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX0+ <30>
P_GFX_RXP10 P_GFX_TXP10
PCIE_GTX_C_FRX_N10 P8 P1 PCIE_FTX_GRX_N10 C38 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N10 PCIE_FTX_GRX_N10 R6 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX0- <30>
P_GFX_RXN10 P_GFX_TXN10
PCIE_GTX_C_FRX_P11 N5 P4 PCIE_FTX_GRX_P11 C39 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P11 PCIE_FTX_GRX_P11 R7 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TXC+ <30>
P_GFX_RXP11 P_GFX_TXP11
PCIE_GTX_C_FRX_N11 N6 P5 PCIE_FTX_GRX_N11 C40 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N11 PCIE_FTX_GRX_N11 R8 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TXC- <30>
P_GFX_RXN11 P_GFX_TXN11
PCIE_GTX_C_FRX_P12 N8 N2 PCIE_FTX_GRX_P12 C41 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P12
P_GFX_RXP12 P_GFX_TXP12
PCIE_GTX_C_FRX_N12 N9 N3 PCIE_FTX_GRX_N12 C42 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N12
P_GFX_RXN12 P_GFX_TXN12
PCIE_GTX_C_FRX_P13 M7 M2 PCIE_FTX_GRX_P13 C43 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P13
P_GFX_RXP13 P_GFX_TXP13
PCIE_GTX_C_FRX_N13 M8 M1 PCIE_FTX_GRX_N13 C44 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N13
P_GFX_RXN13 P_GFX_TXN13
PCIE_GTX_C_FRX_P14 L5 M4 PCIE_FTX_GRX_P14 C45 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P14
P_GFX_RXP14 P_GFX_TXP14
PCIE_GTX_C_FRX_N14 L6 M5 PCIE_FTX_GRX_N14 C46 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N14
P_GFX_RXN14 P_GFX_TXN14
PCIE_GTX_C_FRX_P15 L8 L2 PCIE_FTX_GRX_P15 C47 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P15
P_GFX_RXP15 P_GFX_TXP15
PCIE_GTX_C_FRX_N15 L9 L3 PCIE_FTX_GRX_N15 C48 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N15
P_GFX_RXN15 P_GFX_TXN15
PCIE_FRX_C_LANTX_P0 AC5 AD4 PCIE_FTX_LANRX_P0 C49 1 2 0.1U_0402_16V7K
<34> PCIE_FRX_C_LANTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_FTX_C_LANRX_P0 <34>
PCIE_FRX_C_LANTX_N0 AC6 PCIE_FTX_LANRX_N0 C50
LAN
<34> PCIE_FRX_C_LANTX_N0 P_GPP_RXN0 P_GPP_TXN0 AD5 1 2 0.1U_0402_16V7K PCIE_FTX_C_LANRX_N0 <34>
3 PCIE_FRX_WLANTX_P1 PCIE_FTX_WLANRX_P1 C51 3
<33> PCIE_FRX_WLANTX_P1 AC8 P_GPP_RXP1 P_GPP_TXP1 AC2 1 2 0.1U_0402_16V7K PCIE_FTX_C_WLANRX_P1 <33>
PCIE_FRX_WLANTX_N1 PCIE_FTX_WLANRX_N1 C52
WLAN
2 0.1U_0402_16V7K
GPP
<33> PCIE_FRX_WLANTX_N1 AC9 P_GPP_RXN1 P_GPP_TXN1 AC3 1 PCIE_FTX_C_WLANRX_N1 <33>
PCIE_FRX_JETTX_P2 AB7 AB2 PCIE_FTX_JETRX_P2 C53 1 2 0.1U_0402_16V7K
<33> PCIE_FRX_JETTX_P2 P_GPP_RXP2 P_GPP_TXP2 PCIE_FTX_C_JETRX_P2 <33>
PCIE_FRX_JETTX_N2 PCIE_FTX_JETRX_N2 C54
JET
<33> PCIE_FRX_JETTX_N2 AB8 P_GPP_RXN2 P_GPP_TXN2 AB1 1 2 0.1U_0402_16V7K PCIE_FTX_C_JETRX_N2 <33>
AA5 AB4
AA6
P_GPP_RXP3 P_GPP_TXP3
AB5
FAN Control Circuit +3VS
P_GPP_RXN3 P_GPP_TXN3
1
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