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A B C D E
1 1
PWWHA
2 Delhi 10RG 2
LA-7201P REV 1.0 Schematic
3
Intel Processor(Sandy Bridge) / PCH(Cougar Point) 3
2011-01-31 Rev 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 1 of 53
A B C D E
A B C D E
Fan Control Circuit
Intel CPU page 5
PCI-Express 8X 2.5GHz Sandy Bridge
1
rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1
37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12
page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s
FDI X8 DMI X4
2.7GT/s 5GT/s
USB Port 2IN1 RTS5137 Int. Camera
VGA Board(GDDR3)
USB port 0,1 USB port 10 USB port 11
USB page 31 page 34 page 19
CRT
5V 480MHz
NVIDIA N12M-GE-S-B1 BGA 533P page 20
2 2
page 13,14,15,16,17,18 PCIeMini Card
USB WiMax USB port 9
5V 480MHz page 32
LVDS Conn.
page 19
PCIe 1x PCIeMini Card
1.5V 5GT/s
WLAN PCIe port 2
Intel PCH page 32
Cougar Point - M
RTL8105E 10/100M SATA port 0 SATA HDD
RJ45 PCIe 1x 5V 6GHz(600MB/s) SATA port 0
page 33 PCIe port 1 1.5V 5GT/s page 31
page 33
FCBGA-989
25mm*25mm SATA port 2 SATA ODD
5V 3GHz(300MB/s) SATA port 2
3
page 31 3
page 21,22,23,24,25,26,27,28,29
HD Audio 3.3V 24MHz
LPC BUS
3.3V 33 MHz
RTC CKT. HDA Codec
page 21 ALC259-VB5-GR
SPI ROM Debug Port ENE KB930 QFN 48P page 36
page 39 page 38
(4MB) 21
page
DC/DC Interface CKT.
page 41
Touch Pad Int.KBD EC ROM Ext. SPK Conn HP Conn
page 40 page 39
4 Power Circuit DC/DC (128KB) 39 MIC Conn 4
page page 37 page 37 page 37
page 42,43,44,45,46,
47,48,49,50
Security Classification Compal Secret Data Compal Electronics, Inc.
2010/09/03 2012/12/31 Title
Power/B Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 40 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 2 of 53
A B C D E
A B C D E
B+ DESIGN CURRENT 0.1A +3VL
Ipeak=5A, Imax=3.5A, Iocp min=7.9A DESIGN CURRENT 10A +5VALW
SUSP#
DESIGN CURRENT 1.8A +1.8VS
SY8033BDBC
1 SUSP 1
N-CHANNEL DESIGN CURRENT 5.5A +5VS
SI4800
Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 6A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
SUSP AO-3413
TPS51125ARGER N-CHANNEL DESIGN CURRENT 4.5A +3VS
SI4800 VGA_ENVDD
P-CHANNEL DESIGN CURRENT 2A +LCD_VDD
SUSP or 0.75VR_EN# AO-3413
DESIGN CURRENT 0.5A +0.75VS
G2992F1U
2 2
VR_ON
Ipeak=53A, Imax=36A, Iocp min=70A DESIGN CURRENT 53A +CPU_CORE
ISL95831CRZ-T
SUSP#
Ipeak=20A, Imax=14A, Iocp min=26A DESIGN CURRENT 21A +VGA_CORE
TPS51218DSCR
SUSP#
Ipeak=12.5A, Imax=8.75A, Iocp min=21.4A
DESIGN CURRENT 17A +1.05VS_VCCP
TPS5117
VCCPPWRGD
Ipeak=6A, Imax=4.2A, Iocp min=7.76A DESIGN CURRENT 6A +VCCSA
3 3
TPS51117
SYSON
Ipeak=16.5A, Imax=11.55A, Iocp min=21.03A
DESIGN CURRENT 20A +1.5V
TPS51117RGYR SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU
FDS6676AS
SUSP
N-CHANNEL DESIGN CURRENT 0.7A +1.5VS
FDS6676AS
VGA_PWROK#
N-CHANNEL DESIGN CURRENT 3A +1.5V_MEM_GFX
4 4
FDS6676AS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 3 of 53
A B C D E
A B C D E
( O MEANS ON X MEANS OFF )
Voltage Rails
+5VS
+RTCVCC B+ +3VL +5VALW +1.5V
+3VS
+3VALW
+1.8VS
+VSB
1 power +1.5VS 1
plane +1.05VS
+0.75VS
+CPU_CORE
+GFX_CORE
State
BTO Option Table
Function DIS only MINI PCI-E SLOT LAN Camera & Mic
description SLOT1 LAN Camera & Mic
S0 explain WIMAX 10/100M Giga Camera & Mic
O O O O O O
BTO DIS@ WIMAX@ 8105ELDO@ 8105ESWR@ 8111E@ CAM@
2 S1 2
O O O O O O
S3 Function PCH HDMI/Non-HDMI EC Chip Zero ODD
O O O O O X
description 930 or 9012
S5 S4/AC
O O O O X X
explain 930 Complete Simple
S5 S4/ Battery only
O O O X X X BTO Q65R3@ HDMI@/NHDMI@ 930@ 9012@ S9012@ ZODD@
S5 S4/AC & Battery
don't exist
O X X X X X
PCH SM Bus Address
3 3
Power Device HEX Address
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
+3VS WLAN/WIMAX SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
Full ON HIGH HIGH HIGH
S1(Power On Suspend) HIGH HIGH HIGH
EC SM Bus1 Address EC SM Bus2 Address S3 (Suspend to RAM) LOW HIGH HIGH
S4 (Suspend to Disk) LOW LOW HIGH
Power Device HEX Address Power Device HEX Address
S5 (Soft OFF) LOW LOW LOW
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
G3 LOW LOW LOW
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7201P M/B
Date: Friday, February 25, 2011 Sheet 4 of 53
A B C D E
A B C D E
JCPUB
@ Stuff R41 and R42 if do not support eDP
1000P_0402_50V7K 2 1 C487 PM_DRAM_PW RGD_R 100 MHz
@ PROC_SELECT# A28 CLK_CPU_DMI +1.05VS_VCCP
BCLK CLK_CPU_DMI 22
MISC
CLOCKS
1000P_0402_50V7K 2 1 C488 H_PW RGOOD H_SNB_IVB# C26 A27 CLK_CPU_DMI#
25 H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_DMI# 22
120 MHz CLK_CPU_DPLL# R42 1 2 1K_0402_5%
T1 PAD TP_SKTOCC# AN34 SKTOCC# CLK_CPU_DPLL CLK_CPU_DPLL R41 1
DPLL_REF_SSCLK A16 2 1K_0402_5%
A15 CLK_CPU_DPLL#
DPLL_REF_SSCLK#
1 1
T2 PAD H_CATERR# AL33 CATERR#
THERMAL
H_PECI AN33 R8 H_DRAMRST#
38 H_PECI PECI SM_DRAMRST# H_DRAMRST# 7
DDR3
MISC
R450
38,43 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R1437 2 1 140_0402_1% DDR3 Compensation Signals
56_0402_5% PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R1438 2
SM_RCOMP[1] A5 1 25.5_0402_1% Layout Note:Place these
A4 SM_RCOMP_2 R1439 2 1 200_0402_1% resistors near Processor
SM_RCOMP[2]
H_THERMTRIP# AN32
26 H_THERMTRIP# THERMTRIP#
Remove R14(o ohm) for HW Review demand AP29 XDP_PRDY#_R R1 1 @ 2 0_0402_5% XDP_PRDY#
PRDY# XDP_PREQ#_R R2 1 @
PREQ# AP27 2 0_0402_5% XDP_PREQ#
AR26 XDP_TCK_R R4 1 @ 2 0_0402_5% XDP_TCK
TCK
PWR MANAGEMENT
XDP_TMS_R R6 1 @ 2 0_0402_5% XDP_TMS
JTAG & BPM
TMS AR27
+1.05VS_VCCP H_PM_SYNC AM34 AP30 XDP_TRST#_R R7 1 @ 2 0_0402_5% XDP_TRST# Routed as a single daisy chain
23 H_PM_SYNC PM_SYNC TRST#
AR28 XDP_TDI_R R8 1 @ 2 0_0402_5% XDP_TDI
R47 TDI
2 1 62_0402_5% H_PROCHOT#
TDO AP26 XDP_TDO_R R10 1 @ 2 0_0402_5% XDP_TDO
26 H_PW RGOOD H_PW RGOOD AP33 R36
UNCOREPWRGOOD
1 2 +3VS
2 1K_0402_5% 2
R51 2 1 10K_0402_5% H_PW RGOOD AL35 XDP_DBRESET#_R R11 1 @ 2 0_0402_5% XDP_DBRESET#
DBR# XDP_DBRESET# 23
PM_SYS_PW RGD_BUF 1 2 PM_DRAM_PW RGD_R V8
R454 130_0402_5% SM_DRAMPWROK
AT28 XDP_BPM#0_R R12 1 @ 2 0_0402_5% XDP_BPM#0
BPM#[0] XDP_BPM#1_R R13 1 @ 0_0402_5% XDP_BPM#1
BPM#[1] AR29 2
AR30 XDP_BPM#2_R R15 1 @ 2 0_0402_5% XDP_BPM#2
BUF_CPU_RST# BPM#[2] XDP_BPM#3_R R18 1 @ 0_0402_5% XDP_BPM#3
AR33 RESET# BPM#[3] AT30 2
PS3@ C93 AP32
0.1U_0402_16V4Z +3VALW +1.5V_CPU BPM#[4]
BPM#[5] AR31
2 1 AT31
BPM#[6]
FAN Control Circuit (RPM and PWM)
1
U10 AR32
74AHC1G09GW _TSSOP5 BPM#[7]
5
PS3@ R312 PS3@ R339 +5VS JFAN2 @
1 21 200_0402_5% 1A +FAN2 1
P
23,38 PM_PW ROK B 1
0_0402_5% 4 PM_SYS_PW RGD_BUF PU/PD for JTAG signals 2
2
O Sandy Bridge_rPGA_Rev0p61 @ 2
23 DRAMPW ROK 2 A 2 2 3 3
G
1
+1.05VS_VCCP C13 C15
R340 XDP_TMS_R R28 2 1 51_0402_5% 10U_0805_10V6K 1000P_0402_50V7K 4
3
39_0402_5% @ GND
5 GND
R384 @ XDP_TDI_R R29 1 1
2 1 51_0402_5% U1
1 2 0_0402_5% 1 8 ACES_85204-0300N
1 2
W PS3@ XDP_TDO R30 EN GND
D 2 1 51_0402_5% 2 VIN GND 7
+FAN2 3 6 R24 10K_0402_5%
SUSP Q5 XDP_TCK_R R31 VOUT GND
9,32,41,47 SUSP 2 2 1 51_0402_5% 38 EN_DFAN1 4 VSET GND 5 2 1 +3VS
G 2N7002_SOT23-3 10mil 1
S @ XDP_TRST#_R R32 2 1 51_0402_5% APL5607KI-TRG_SO8 FAN_SPEED1
3
C17 1
10U_0805_10V6K C14
3 2 0.01U_0402_25V7K 3
@
JXDP 2
Buffered Reset to CPU XDP Connector XDP_PREQ#
XDP_PRDY#
1
2
@
+3VS 3
XDP_BPM#0 4 +3VS
XDP_BPM#1 5
6
FAN Control Circuit
1
PLT_RST# 13,25,32,33,35,38,39
1 0.1U_0402_16V4Z XDP_BPM#2 7
C84 XDP_BPM#3 8 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo