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A B C D E
1 1
Compal Confidential
2 2
PBL60 Schematics Document
AMD APU Zacate-FT1 + FCH Hudson-M1 + GPU Seymour XT-M2
3
2010-02-15 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P01-Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7322P
Date: Thursday, February 17, 2011 Sheet 1 of 47
A B C D E
A B C D E
Compal confidential
File Name : LA-7322P
AMD Seymour-XT
DDR3 VRAM PCI-E GPP x4 GEN2
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
1 512M/1G AMD Brazos APU 1
Single Channel page 8,9
64*16/128*16 *4 BANK 0, 1, 2, 3
page 17 ~ 24 FT1 1.5V DDRIII
LVDS(UMA & PX)
BGA 413-Ball
LVDS Conn. 19mm x 19mm
page 10
HDMI Conn. HDMI(UMA & PX)
page 11
CRT Conn. CRT(UMA & PX)
page 10 page 5,6,7
UMI Gen.1 x4
Port 0
2.5GT/s per lane SATA HDD Conn.
page 29
SATA Port 1
SATA ODD Conn.
2
page 29 2
Hudson M1
PCI-E 2.0 x1 2Channel Speaker
BGA 605-Ball
page 26
23mm x 23mm
AZALIA Audio Codec Audio Jacks X 2
Port 1 Port 0
ALC269 (Headphone, MIC)
page 26 page 26
Mini Card-1 WLAN LAN(GbE) USB2.0 DMIC
(With Bluetooth) RTL8111E page 10
page 28 page 25 page 12 ~ 16
Port 0
USB Conn.
page 32
Port 1
3 RJ45 LPC BUS USB Conn. 3
page 32
page 25
Port 5
USB Conn.
ENE KB930 (LS-7322P)
page 30 Port 2
Camera
page 10
Port 3
Mini Card WLAN
(With Bluetooth)28
page
LS-7326P Port 4
Card Reader
Power BD Touch Pad SPI ROM Int.KBD
page 31 page 30 page 31
RTS5137 page 27
LS-7322P
4 Audio BD 4
Thermal Sensor
page 18 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P02-Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7322P
Date: Thursday, February 17, 2011 Sheet 2 of 47
A B C D E
A B C D E
Voltage Rails FCH Hudson-M1 Brazos FCH Hudson-M1
Power Plane Description S1 S3 S5 USB Port List PCIE Port List SATA Port List
VIN Adapter power supply (19V) N/A N/A N/A USB1.1 PCIE0 SATA0 HDD
B+ AC or battery power rail for power circuit. N/A N/A N/A
Port0 NC PCIE1 SATA1 ODD
APU
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF GPU
+APU_CORE_NB 1.0V switched power rail ON OFF OFF Port1 NC PCIE2 PCIE x4 SATA2 NC
1 1
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
USB2.0 PCIE3 SATA3 NC
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
+1.0VS 1.0V switched power rail for NB VDDC & VGA ON OFF OFF Port0 JUSB1 PCIE0 LAN SATA4 NC
+1.1VS 1.1VS switched power rail ON OFF OFF
Port1 JUSB2 PCIE1 WLAN SATA5 NC
FCH
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON* Port2 Camera PCIE2 NC
+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF
Port3 JMINI(WLAN) PCIE3 NC
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON* Port4 Card Reader
+5VS 5V switched power rail ON OFF OFF
Port5 JUSB3
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON Port6 NC
+1.1VALW 1.1V always on power rail ON ON ON*
Port7 NC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port8 NC
2 Port9 NC 2
SMBUS Control Table
Port10 NC
SOURCE MIINI1 BATT APU FCH SODIMM VRAM
Port11 NC
Port12 NC
EC_SMB_CK1
EC_SMB_DA1
KB930 X V X X X X Port13 NC
EC_SMB_CK2
EC_SMB_DA2
KB930 X X V V X V
FCH_SMCLK0
FCH_SMDAT0
FCH
(+3VS) V X X X V X SCL0,
SCL1,
SDA0
SDA1
(Primary SMBUS in the S0 domain)
(Secondary SMBUS supporting ASF)
SCL2, SDA2 (Primary SMBUS in the S5 domain)
SCL3, SDA3 (Primary low-voltage SBMBUS for Processor TSI)
FCH_SMCLK3 FCH
FCH_SMDAT3 (+3VALW) X X V X X X SCL4, SDA4 (Primary SMBUS in the S5 domain)
3 3
L01 : 16G@/VGA@/LS@/X76@L03
L02 : 16G@/UMA@/LS@
L03 : 15G@/VGA@/LS@/X76@L03
L04 : 15G@/UMA@/LS@
: etoN lobmyS L05 : 16G@/VGA@/LS@/X76@L01
L06 : 15G@/VGA@/LS@/X76@L01
BOM Structure dnuorG latigiD snaem : L07 : 1G@/VGA@/LS@/X76@L03
15G@: 1.5G CPU (E240)
16G@: 1.6G CPU (E350) L08 : 1G@/UMA@/LS@
1G@ : 1G CPU (C50) dnuorG golanA snaem : L09 : 1G@/VGA@/LS@/X76@L01
UMA@ : APU output.
4 VGA@ : GPU used. 4
LS@ : Level shift used.
X76@L01 :VRAM 1G.
X76@L03 :VRAM 512M.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P03-Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7322P
Date: Thursday, February 17, 2011 Sheet 3 of 47
A B C D E
5 4 3 2 1
Power-Up/Down Sequence
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.
2. VDDR3 should ramp-up before or simultaneously with VDDC.
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. D
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)
VDDR3(3.3VSG) Note: Do not drive any IOs before VDDR3 is ramped up.
PCIE_VDDC(1.0V)
C
VDDR1(1.5VSG) C
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PE_GPIO0 PE_EN
PERSTb BIF_VDDC
PE_GPIO1
REFCLK PX_mode
B B
MOS
Straps Reset
SI4800
Straps Valid Regulator
Global ASIC Reset
Regulator
SI4800
T4+16clock
PWRGOOD
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P04-dGPU Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7322P
Date: Thursday, February 17, 2011 Sheet 4 of 47
5 4 3 2 1
5 4 3 2 1
+1.8VS U22B
DISPLAYPORT 1
A8 H3 R398 1 2 150_0402_1%
11 APU_HDMI_TX2P TDP1_TXP0 DP_ZVSS
DP MISC
11 APU_HDMI_TX2N B8 TDP1_TXN0
G2 APU_ENBKL 10
R399 1K_0402_5% APU_SVC DP_BLON
1 2 11 APU_HDMI_TX1P B9
TDP1_TXP1 DP_DIGON
H2 APU_ENVDD 10
R400 1 2 1K_0402_5% APU_SVD A9 H1
D 11 APU_HDMI_TX1N TDP1_TXN1 DP_VARY_BL APU_BLPWM 10 D
R142 2 1 300_0402_5% APU_RST#
R401 2 1 300_0402_5% APU_PWRGD D10
TEST_25_L 11 APU_HDMI_TX0P TDP1_TXP2 APU_HDMI_CLK
R402 1 2 510_0402_1% C10 B2
11 APU_HDMI_TX0N TDP1_TXN2 TDP1_AUXP APU_HDMI_CLK 11
R141 1 2 1K_0402_5% TEST36 C2 APU_HDMI_DATA
TDP1_AUXN APU_HDMI_DATA 11
11 APU_HDMI_CLKP A10
TDP1_TXP3
11 APU_HDMI_CLKN B10 C1 APU_HDMI_HPD 11
TDP1_TXN3 TDP1_HPD
C237 @ 0.01U_0402_25V7K B5 A3 APU_LCD_CLK
10 APU_TXOUT2+ LTDP0_TXP0 LTDP0_AUXP APU_LCD_CLK 10
APU_RST# APU_LCD_DATA
DISPLAYPORT 0
1 2 10 APU_TXOUT2- A5 B3 APU_LCD_DATA 10
C238 @ 0.01U_0402_25V7K LTDP0_TXN0 LTDP0_AUXN
1 2 APU_PWRGD D6 D3 R406 1 2 100K_0402_5% +5VS
10 APU_TXOUT1+ LTDP0_TXP1 LTDP0_HPD
10 APU_TXOUT1- C6
LTDP0_TXN1
C12 APU_CRT_R 10
DAC_RED R407 1
10 APU_TXOUT0+ A6 LTDP0_TXP2 DAC_REDB D13 2 150_0402_1%
10 APU_TXOUT0- B6 LTDP0_TXN2 DAC_GREEN A12 APU_CRT_G 10
+3VS B12 R408 1 2 150_0402_1%
DAC_GREENB
D8 A13
VGA DAC
APU_PROCHOT# 10 APU_TXCLK+ LTDP0_TXP3 DAC_BLUE APU_CRT_B 10
R410 1 2 1K_0402_5% C8 B13 R409 1 2 150_0402_1%
10 APU_TXCLK- LTDP0_TXN3 DAC_BLUEB
12 APU_CLKP V2 CLKIN_H DAC_HSYNC E1 APU_CRT_HSYNC 10
12 APU_CLKN V1 CLKIN_L DAC_VSYNC E2 APU_CRT_VSYNC 10
CLK
12 APU_DISP_CLKP D2 DISP_CLKIN_H DAC_SCL F2 APU_CRT_DDC_SCL 10
R411 1 2 1K_0402_5% APU_ALERT#_R D1 D4
12 APU_DISP_CLKN DISP_CLKIN_L DAC_SDA APU_CRT_DDC_SDA 10
R143 1 2 1K_0402_5% APU_SIC J1 D12 R144 1 2 499_0402_1%
43 APU_SVC SVC DAC_ZVSS
43 APU_SVD J2 SVD
SER
R414 1 2 1K_0402_5% APU_SID R1 PAD T66
APU_SIC TEST4
P3 R2 PAD T67
APU_SID SIC TEST5
P4 R6
SID TEST6
TEST14 T5 PAD T68
T3 E4 TEST15 R415 1 @ 2 1K_0402_5%
C 12 APU_RST# RESET_L TEST15 C
12 APU_PWRGD T4 K4
CTRL
PWROK TEST16
TEST17 L1
R169 1 2 0_0402_5% APU_PROCHOT# U1 L2 TEST18 R416 1 2 1K_0402_5%
30 EC_THERM# APU_THERMTRIP# U2 PROCHOT_L TEST18 TEST19
R168 1 @ 2 0_0402_5% M2 R417 1 2 1K_0402_5%
TEST
12 FCH_PROCHOT# APU_ALERT#_R THERMTRIP_L TEST19 TEST25_H
T2 K1 R418 1 2 510_0402_1%
ALERT_L TEST25_H TEST_25_L
TEST25_L K2
APU_TDI N2 L5
APU_TDO TDI TEST28_H
N1 M5
APU_TCK TDO TEST28_L TEST31
P1 M21 PAD T73
TCK TEST31
JTAG
APU_TMS P2 J18 TEST33_H C516 1 2 0.1U_0402_16V4Z R420 1 2 51_0402_1%
APU_TRST# TMS TEST33_H TEST33_L C517 1
T93PAD M4 J19 2 0.1U_0402_16V4Z R421 1 2 51_0402_1%
APU_DBRDY TRST_L TEST33_L Delete Test point for layout limitation
T94PAD M3 U15
Close to APU APU_DBREQ# DBRDY TEST34_H 20100917
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