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A B C D E
1 1
Compal Confidential
2 2
QIWY4 M/B Schematics Document
Intel IVY Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13X
3 2011-12-23 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY4 LA-8002P
Date: Monday, January 16, 2012 Sheet 1 of 64
A B C D E
A B C D E
Compal confidential
File Name : Y580
Chief River
nVIDIA N13E-GE
Intel
1 PCI-E X16 1
IVY Bridge DDR3-SO-DIMM X2
Gen 1/2/3
VRAM 64*32 Processor BANK 0, 1, 2, 3
GDDR5*8 Socket-rPGA989 Dual Channel UP TO 16G
37.5mm*37.5mm DDR3-1333(1.5V)
HDMI DDR3-1600(1.5V)
HDMI1.4a
SATA3.0 HDD CONN
CONN FDI *8 DMI2 *4
100MHz 100MHz SATA3.0 HDD (SSD)
optimus 2012 2.7GT/s 5GT/s
CRT Connector 6*SATA SATA ODD CONN
(port0,1 Support SATA3)
2
optimus 2012 Intel 4*USB3.0 2
LVDS
Connector Panther Point
14*USB2.0
BlueTooth CONN
PCI Express USB(WiMAX)
PCH
6*PCI-E x1 CMOS Camera
Mini card Slot 1 PCI-E(WLAN) FCBGA 989 Balls
WLAN/WiMAX 25mm*25mm USB PORT 3.0 x2(Left)
PCI Express SATA(SSD) HD Audio WLAN/WiMAX
Mini card Slot 2
SSD USB PORT 2.0 x1(Right)
PCI Express SPI ROM LPC BUS TV
Mini card Slot 3 BIOS
3 TV
Card Reader USB PORT 3.0 x1 (Right) 3
EC with USB charger
PCI-E
USB
JBM389C Audio Board
SD/MMC/MS/XD ENE KB9012
Audio Board
LAN(Gbe)
WLAN/WiMAX ATHEROS
AR8161/AR8151
Int.KBD
2Channel Speaker
TV Touch Pad
RJ45 CONN Audio Codec Array Digital MIC
RealTek
Sub-borad ALC269-VC
Thermal Sensor Audio Jacks
4
POWER BOARD Stereo 4
EMC1403/2103
HeadPhone Output
Microphone Input
Audio Board
Function Board
Security Classification Compal Secret Data Compal Electronics, Inc.
2010/11/30 2011/12 Title
Audio Board Issued Date Deciphered Date
MB Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 2 of 64
A B C D E
A B C D E
Voltage Rails
SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
power +VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
plane +V1.5S_VCCP
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1
+CPU_CORE 1
+5VALW +1.5V
+VGA_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+B
+GFX_CORE
+3VALW S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.8VS
+1.05VS
State
+0.75VS BOARD ID Table Board ID / SKU ID Table for AD channel
+3.3VS_VGA Vcc 3.3V +/- 5%
+1.5VS_VGA
Board ID PCB Revision
Ra/Rc/Re 10K +/- 5%
+1.05VS_VGA
0 0.1 Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Project
1 QIWY3
0 0 0 V 0 V 0 V EVT
2 QIWY3
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
3
2 18K +/- 5% 0.436 V 0.503 V 0.538 V QIWY3 PVT
S0 4
O O O O 3 33K +/- 5% 0.712 V 0.819 V 0.875 V QIWY3 MP
5
4 56K +/- 5% 1.036 V 1.185 V 1.264 V QIWY4 EVT
6 QIWY4
S3
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
O O O X 7 QIWY4
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PVT
2 7 NC 2.500 V 3.300 V 3.300 V QIWY4 MP 2
S5 S4/AC
O O X X USB Port Table BOM Structure Table
S5 S4/ Battery only
4 External
O X X X USB 2.0 USB 3.0 Port USB Port BOM Structure BTO Item
OPTI@ OPTIMUS part
S5 S4/AC & Battery
1 0 USB Port (Right Side) HDMI part
X X X X HDMI@
don't exist 2 1 TV module part
XHCI TV@
3 2 USB Port (Left Side) USB charger part
CHG@
4 3 USB Port (Left Side) No USB charger part
elbaT lortnoC SUBMS EHCI1 NOCHG@
4 Blue Tooth part
lamrehT BT@
NALW 5 Camera CMOS Camera part
ECRUOS AGV TTAB 2109EK NAWW MMIDOS HCP rosneS CMOS@
6 AR8161 LAN part
8161@
1KC_CE_BMS 7 AR8151 LAN part
2109BK X V X X X X X 8151@
1AD_CE_BMS WLAV3+ WLAV3+ 8 AR8161 LAN surge part
8161S@
2KC_CE_BMS 9 USB Port (Right Side) AR8151 LAN surge part
2109BK X X X X X X V 8151S@
2AD_CE_BMS WLAV3+ SV3+ 10 Mini Card(WLAN) AR8151&8161 LAN surge part
EHCI2 SURGE@
KLCBMS 11 X76 P/N for AR8161
HCP X X X V V X X 61@
3 ATADBMS WLAV3+ SV3+ SV3+ 12 Mini Card(TV) X76 P/N for AR8151 3
51@
KLC0LMS 13 Blue Tooth X76 Level part for VRAM
HCP X X X X X X X X76@
ATAD0LMS WLAV3+ X76 P/N for Samsun VRAM 1G
PCIE PORT LIST S1G@
KLC1LMS X76 P/N for Samsun VRAM 2G
HCP V X V X X V X S2G@
ATAD1LMS WLAV3+ SV3+ SV3+ SV3+ Port Device X76 P/N for Hynix VRAM 1G
H1G@
1 LAN H2G@ X76 P/N for Hynix VRAM 2G
Address
2 WLAN GL@ N13P-GL part
EC SM Bus1 address EC SM Bus2 address
3 TV GT@ N13P-GT part
Device Device Address 4 Card Reader GE@ N13E-GE part
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb 5 GTGE@ N13P-GT&N13E-GE common part
6 GC6@ NV CG6 support part
7 NOGC6@ NV no CG6 support part
8 1403@ EMC1403 thermal part
PCH SM Bus address
2103@ EMC2103 thermal part
Device Address KBL@ K/B Light part
DDR DIMM0 1001 000Xb ME@ ME part
4 4
DDR DIMM2 1001 010Xb @ Unpop
ZZZ1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
DA80000Q900
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY4 LA-8002P
Date: Monday, January 16, 2012 Sheet 3 of 64
A B C D E
5 4 3 2 1
Hot plug detect for IFP link C
Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO0 OUT - GPU VID4 N13X
128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - GPU VID3 GDDR5
GPIO2 OUT N/A
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT N/A
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT N/A ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT - GPU VID1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - GPU VID2 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT N/A
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 I/O - Thermal Catastrophic Over Temperature STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - GC6 event
Device ID
GPIO10 OUT - Memory VREF Control N13P-GT
(28nm) 0x0FDB
GPIO11 OUT - GPU VID0
C
N13E-GE C
(28nm) 0x0FDB
GPIO12 IN AC Power Detect Input (10K pull High)
N13P-GL1
GPIO13 OUT - GPU VID5 (40nm) 0x0DE9
GPIO14 OUT N/A
GPIO15 IN N/A (100K pull low) GPU ROM_SO ROM_SCLK STRAP4 STRAP3 STRAP2 STRAP1 STRAP0
GPIO16 OUT N/A N13P-GT PU 10K PU 5K PD 45K PD 5K PD 10K PD 35K PU 45K
GPIO17 IN N/A N13E-GE PU 10K PU 5K PD 45K PD 5K PD 25K PD 35K PU 45K
GPIO18 IN N/A N13P-GL PD 10K PD 15K NC NC PU 10K PD 45K PU 45K
GPIO19 IN N/A
GPU N13P-GT N13E-GE N13P-GL
FB Memory (GDDR5) ROM_SI ROM_SI ROM_SI
Samsung K4G10325FG-HC04
B
+3VS_VGA 2500MHz B
32Mx32 PD 45K PD 45K PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K PD 35K PD 35K
tFBVDDQ >0
Samsung K4G20325FG-HC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K PD 30K PD 30K
1. all power rail ramp up time should be larger than 40us
Hynix H5GQ2H24MFR-T2C
2500MHz
64Mx32 PD 25K PD 25K PD 25K
Other Power rail
+3VS_VGA
A A
Tpower-off <10ms
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY4 LA-8002P
Date: Monday, January 16, 2012 Sheet 4 of 64
5 4 3 2 1
5 4 3 2 1
D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R1
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
<16> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23>
<16> DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N15
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14
PEG_RX#[1] M35
<16> DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N13
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
<16> DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 PEG Static Lane Reversal - CFG2 is for the 16x
A24 J32 PCIE_CRX_GTX_N11
<16> DMI_CRX_PTX_P2
DMI
DMI_RX[2] PEG_RX#[4] PCIE_CRX_GTX_N10
<16> DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
PEG_RX#[6] PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 F21 DMI_TX#[2] PEG_RX#[9] F35
D21 E34 PCIE_CRX_GTX_N5 0:Lane Reversed
<16>
<16>
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 G22
DMI_TX#[3]
DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
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