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A B C D E
1 1
Compal Confidential
2 2
QAWGH Schematics Document
AMD APU Trinity FS1r2 + FCH Hudson-M3 + GPU Seymourr XT
2011-10-07
3
REV:0.1 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 1 of 51
A B C D E
A B C D E
ZZZ QAWGH
Compal confidential
File Name : QAWGH LA8611P LS7986P CardReader/B
LS7982P USB/B
DA_PCB
DA80000S600
LS7983P PWR/B
AMD Seymour XT LS8612P LED/B
LS7985P ODD/B
VRAM PCIE x 16 Gen2 LS8617P Cap Sensor/B
1 1
64M16/128M16 Memory BUS(DDRIII)
DDR3 x 4 AMD FS1r2 APU Dual Channel
page 17 ~ 23
1.5V DDRIII 1866 204pin DDRIII-SO-DIMM X2
DP Port0 Trinity BANK 0, 1, 2 page 10,11
LVDS
translator
uPGA 722 pin
RTDS2132S HDMI Conn. DP Port2 35mm x 35mm
page 24 page 26
DP Port1 page 5,~9
4 * x1 PCI-E 2.0 x4 UMI Gen. 1
LVDS Conn. 2.5GT/s per lane
page 25 GPP1 GPP0 2Channel Speaker
page 30
LAN
AR8161/8162
2 AZALIA Audio Codec Internal MIC 2
page 28~29 page 30
Hudson M3 CX20671-21Z
page 30
PCI Express USB(WiMAX) uFCBGA-656 Audio Jacks
CRT Conn. FCH CRT (VGA DAC)
Mini Card Slot 1 page 27 24.5mm x 24.5mm Sub-board
4*USB3.0,10*USB2.0
WLAN/WiMAX page 32 4 * x1 PCI-E 2.0
CMOS Camera page 25
page 12~16 6*SATA serial
BlueTooth Conn page 31
USB Port 3.0 x2(Left) page 37,38
LPC Bus
SPI ROM USB Port 2.0 x 1 (Right) Sub-board
page 13
RTS5178
3
EC Card Reader 2 in 1 Conn. 3
Cap Sensor USB 2.0 x 1 Sub-board SD/SDXC/MMC
Sub-board ENE KB930/ KB9012
page 34
Touch Pad Int. KBD
page 35 page 35 SATA0 SATA 3.0 HDD Conn.
page 31
SATA1 SATA ODD Conn.
page 31
Thermal Sensor
EMC1403
4
page 32 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 2 of 51
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Voltage Rails
Power Plane Description S1 S3 S5 FCH Hudson-M2/3 Comal FCH Hudson-M2/3 FCH Hudson-M2/3
VIN Adapter power supply (19V) N/A N/A N/A
SATA Port List PCIE Port List USB Port List USB OC PIN
B+ AC or battery power rail for power circuit. N/A N/A N/A SATA0 NC PCIE0 LAN USB1.1 USB_OC0# USB3.0 (LP1, LP2)
+APU_CORE Core voltage for APU ON OFF OFF
SATA1 HDD PCIE1 WLAN Port0 NC USB_OC1# USB2.0 (RP1)
APU
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF
1 1
+1.5V 1.5V power rail for APU VDDIO and DDR ON ON OFF SATA2 ODD PCIE2 NC Port1 NC USB_OC2# USB2.0 (RP2)
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
+1.2VS 1.2V (VDDR, VDDP) switched power rail for APU ON OFF OFF
SATA3 NC PCIE3 NC USB2.0 USB_OC3# NC
+2.5VS 2.5V for APU VDDA ON OFF OFF SATA4 NC PCIE0 NC Port0 Right USB1 USB_OC4# NC
+1.1VALW 1.1V switched power rail for FCH ON ON ON*
SATA5 NC PCIE1 NC Port1 Right USB2 USB_OC5# NC
FCH
+1.1VS 1.1V switched power rail for FCH ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF PCIE2 NC Port2 Mini PCIE USB_OC6# NC
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF
+1.5VGS 1.5V switched power rail ON OFF OFF
PCIE3 NC Port3 USB Camera USB_OC7# NC
+1.8VGS 1.8V switched power rail ON OFF OFF Port4 BT
+1.0VGS 1.0V switched power rail for VGA ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
Port5 Card Reader
+3V_LAN 3.3V power rail for LAN ON ON ON* Port6 NC
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
Port7 NC
+5VS 5V switched power rail ON OFF OFF Port8 NC
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
Port9 NC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Port10 USB3.0 LP1
Port11 USB3.0 LP2
Port12 NC
EC SM Bus1 address EC SM Bus2 address BOM Structure Port13 NC
Device Address HEX Device Address HEX UMA@ : UMA only
Smart Battery 0001-011xb 15H EMC1403(VGA, DDR,WLAN) 1001-101xb 9AH PX@ : DIS muxluss
SB-TSI (default) 1001-100xb 98H CMOS@ : USB camera
VGA Thermal 1000-001xb 82H HDMI@ : HDMI function
Cap Sensor 1000-0000b 80H nonHDMI@ : w/o HDMI function
RTDS2132S-E 1010-1000b A8H BT@ : BT function
ME@ : ME components
X76@ : VRAM
3 3
45@ : 45 Level
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
PX4@ : PX4
PX5@ : PX5
Device Address HEX 8162@ : 10/100 LAN
GIGA@ : giga LAN
14@ : G 14"
15@ : G 15"
BBH@ : Best Buy high-end
nonBBH@ : non Best Buy high-end
SM Bus Controller 1 (FCH_SMB0)
AN@ : Apple & Nokia combo
A@ : Apple only
Device Address HEX
DDR DIMM1 (FCH_SMB0) 1001-000xb 90H
DDR DIMM2 (FCH_SMB0) 1001-001xb 92H
WLAN (FCH_SMB0)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 3 of 51
A B C D E
5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PE_GPIO0 (PXS_RST#) : Low > Reset dGPU ; High >Normal operation
PE_GPIO1 (PXS_PWREN) : Low > dGPU Power OFF ; High > dGPU Power ON
"Seymour" has the following requirements with regards to power-supply sequencing
to avoid damaging the ASIC: BACO option :
All the ASIC supplies, except for VDDR3, must fully reach their respective PE_GPIO0 (PXS_RST#) : High >Normal operation (dGPU is not reset on BACO mode)
PE_GPIO1 (PXS_PWREN) : Low > dGPU Power OFF ; High > dGPU Power ON (always High)
nominal voltages within 20 ms of the start of the ramp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D ramp up of VDDR3 relative to other power rails. PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA D
The external pull-up resistors on the DDC/AUX signals (if applicable) should DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
ramp up before or after both VDDC and VDD_CT have ramped up. DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC DPLL_PVDD, MPV18, and SPV18
should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 775mA
enabled designs, VDDC must ramp up before VDD_CT at system power up. SPV10
For power down, reversing the ramp-up sequence is recommended
PCIE_VDDC 1.0V OFF ON 1.1A
VDDR3 3.3V OFF ON 60mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 1.2A
VDDR3(3.3VGS) VDDC/VDDCI TBD OFF OFF 28
PCIE_VDDC(1.0V)
PX4.0
C
VDDR1(1.5VGS) C
PE_GPIO0(PXS_RST#) PE_EN BACO Switch
iGPU dGPU
VDDC/VDDCI(1.12V) BIF_VDDC
PE_GPIO1(PXS_PWREN)
VDD_CT(1.8V) PX_mode
+3.3VALW MOS
+3.3VGS
PERSTb 1
B+ Regulator
+1.5VGS
REFCLK +1.5V +1.0VGS
LDO
2 3
Straps Reset
+B Regulator
+VGA_CORE
+5VLAW +1.8VGS
Regulator
5 4
Straps Valid
PWRGOOD
B B
Global ASIC Reset
PX5.0
T4+16clock
PE_GPIO0(PXS_RST#) +VGA_CORE
iGPU dGPU
BIF_VDDC
PE_GPIO1(PXS_PWREN)
+3.3VALW MOS
+3.3VGS Short PX_MODE and PX_PWREN
1
B+ Regulator
+1.5VGS
+1.5V +1.0VGS
LDO
2 3
A
+B Regulator
+VGA_CORE A
+5VLAW +1.8VGS
Regulator
5 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 4 of 51
5 4 3 2 1
A B C D E
<17> PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_P[0..15] <17>
<17> PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N[0..15] <17>
JCPU1A
PCI EXPRESS
PCIE_CRX_GTX_P0 AB8 AB2 PCIE_CTX_C_GRX_P0 C1 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_C_GRX_N0 C2 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_N0
AB7 P_GFX_RXN0 P_GFX_TXN0 AB1 1 2
PCIE_CRX_GTX_P1 AA9 AA3 PCIE_CTX_C_GRX_P1 C3 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_C_GRX_N1 C4 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_N1
AA8 P_GFX_RXN1 P_GFX_TXN1 AA2 1 2
PCIE_CRX_GTX_P2 AA5 Y5 PCIE_CTX_C_GRX_P2 C5 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_C_GRX_N2 C6 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_N2
AA6 P_GFX_RXN2 P_GFX_TXN2 Y4 1 2
1 PCIE_CRX_GTX_P3 PCIE_CTX_C_GRX_P3 C7 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P3 1
Y8 P_GFX_RXP3 P_GFX_TXP3 Y2 1 2
PCIE_CRX_GTX_N3 Y7 Y1 PCIE_CTX_C_GRX_N3 C8 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_P4 C9 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P4
W9 P_GFX_RXP4 P_GFX_TXP4 W3 1 2
PCIE_CRX_GTX_N4 W8 W2 PCIE_CTX_C_GRX_N4 C10 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 P_GFX_RXN4 P_GFX_TXN4 PCIE_CTX_C_GRX_P5 C11 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P5
W5 P_GFX_RXP5 P_GFX_TXP5 V5 1 2
PCIE_CRX_GTX_N5 W6 V4 PCIE_CTX_C_GRX_N5 C12 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 P_GFX_RXN5 P_GFX_TXN5 PCIE_CTX_C_GRX_P6 C13 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P6
V8 P_GFX_RXP6 P_GFX_TXP6 V2 1 2
PCIE_CRX_GTX_N6 PCIE_CTX_C_GRX_N6 PCIE_CTX_GRX_N6
GRAPHICS
V7 V1 C14 PX@ 1 2 0.1U_0402_16V7K
PCIE_CRX_GTX_P7 P_GFX_RXN6 P_GFX_TXN6 PCIE_CTX_C_GRX_P7 C15 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P7
U9 P_GFX_RXP7 P_GFX_TXP7 U3 1 2
PCIE_CRX_GTX_N7 U8 U2 PCIE_CTX_C_GRX_N7 C16 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N7
PCIE_CRX_GTX_P8 P_GFX_RXN7 P_GFX_TXN7 PCIE_CTX_C_GRX_P8 C17 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P8
U5 P_GFX_RXP8 P_GFX_TXP8 T5 1 2
PCIE_CRX_GTX_N8 U6 T4 PCIE_CTX_C_GRX_N8 C18 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N8
PCIE_CRX_GTX_P9 P_GFX_RXN8 P_GFX_TXN8 PCIE_CTX_C_GRX_P9 C19 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P9
T8 P_GFX_RXP9 P_GFX_TXP9 T2 1 2
PCIE_CRX_GTX_N9 T7 T1 PCIE_CTX_C_GRX_N9 C20 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N9
PCIE_CRX_GTX_P10 P_GFX_RXN9 P_GFX_TXN9 PCIE_CTX_C_GRX_P10 C21 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P10
R9 P_GFX_RXP10 P_GFX_TXP10 R3 1 2
PCIE_CRX_GTX_N10 R8 R2 PCIE_CTX_C_GRX_N10 C22 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N10
PCIE_CRX_GTX_P11 P_GFX_RXN10 P_GFX_TXN10 PCIE_CTX_C_GRX_P11 C23 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P11
R5 P_GFX_RXP11 P_GFX_TXP11 P5 1 2
PCIE_CRX_GTX_N11 R6 P4 PCIE_CTX_C_GRX_N11 C24 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N11
PCIE_CRX_GTX_P12 P_GFX_RXN11 P_GFX_TXN11 PCIE_CTX_C_GRX_P12 C25 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P12
P8 P_GFX_RXP12 P_GFX_TXP12 P2 1 2
PCIE_CRX_GTX_N12 P7 P1 PCIE_CTX_C_GRX_N12 C26 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N12
PCIE_CRX_GTX_P13 P_GFX_RXN12 P_GFX_TXN12 PCIE_CTX_C_GRX_P13 C27 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P13
N9 P_GFX_RXP13 P_GFX_TXP13 N3 1 2
PCIE_CRX_GTX_N13 N8 N2 PCIE_CTX_C_GRX_N13 C28 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N13
PCIE_CRX_GTX_P14 P_GFX_RXN13 P_GFX_TXN13 PCIE_CTX_C_GRX_P14 C29 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P14
N5 P_GFX_RXP14 P_GFX_TXP14 M5 1 2
PCIE_CRX_GTX_N14 N6 M4 PCIE_CTX_C_GRX_N14 C30 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N14
PCIE_CRX_GTX_P15 P_GFX_RXN14 P_GFX_TXN14 PCIE_CTX_C_GRX_P15 C31 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P15
M8 P_GFX_RXP15 P_GFX_TXP15 M2 1 2
PCIE_CRX_GTX_N15 M7 M1 PCIE_CTX_C_GRX_N15 C32 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N15
P_GFX_RXN15 P_GFX_TXN15
AE5 AD5 PCIE_CTX_C_DRX_P0 C33 1 2 0.1U_0402_16V7K
<28> PCIE_CRX_DTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_CTX_DRX_P0 <28>
LAN AE6 AD4 PCIE_CTX_C_DRX_N0 C34 1 2 0.1U_0402_16V7K
<28> PCIE_CRX_DTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_CTX_DRX_N0 <28>
AD8 AD2 PCIE_CTX_C_DRX_P1 C35 1 2 0.1U_0402_16V7K
<32> PCIE_CRX_DTX_P1 P_GPP_RXP1 P_GPP_TXP1 PCIE_CTX_DRX_P1 <32>
WLAN AD7 AD1 PCIE_CTX_C_DRX_N1 C36 1 2 0.1U_0402_16V7K
<32> PCIE_CRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_CTX_DRX_N1 <32>
AC9 P_GPP_RXP2 P_GPP_TXP2 AC3
GPP
2 2
AC8 P_GPP_RXN2 P_GPP_TXN2 AC2
AC5 P_GPP_RXP3 P_GPP_TXP3 AB5
AC6 P_GPP_RXN3 P_GPP_TXN3 AB4
AG8 AG2 UMI_TXP0_C C37 1 2 0.1U_0402_16V7K
<12> UMI_RXP0 P_UMI_RXP0 P_UMI_TXP0 UMI_TXP0 <12>
AG9 AG3 UMI_TXN0_C C38 1 2 0.1U_0402_16V7K
<12> UMI_RXN0 P_UMI_RXN0 P_UMI_TXN0 UMI_TXN0 <12>
AG6 AF4 UMI_TXP1_C C39 1 2 0.1U_0402_16V7K
<12> UMI_RXP1 P_UMI_RXP1 P_UMI_TXP1 UMI_TXP1 <12>
AG5 AF5 UMI_TXN1_C C40 1 2 0.1U_0402_16V7K
<12> UMI_RXN1 P_UMI_RXN1 P_UMI_TXN1 UMI_TXN1 <12>
AF7 AF1 UMI_TXP2_C C41 1 2 0.1U_0402_16V7K
<12> UMI_RXP2 P_UMI_RXP2 P_UMI_TXP2 UMI_TXP2 <12>
AF8 AF2 UMI_TXN2_C C42 1 2 0.1U_0402_16V7K
<12> UMI_RXN2 P_UMI_RXN2 P_UMI_TXN2 UMI_TXN2 <12>
AE8 AE2 UMI_TXP3_C C43 1 2 0.1U_0402_16V7K
<12> UMI_RXP3 UMI_TXP3 <12>
UMI
P_UMI_RXP3 P_UMI_TXP3 UMI_TXN3_C C44 0.1U_0402_16V7K
<12> UMI_RXN3 AE9 P_UMI_RXN3 P_UMI_TXN3 AE3 1 2 UMI_TXN3 <12>
+1.2VS 1 2 P_ZVDDP AG11 P_ZVDDP P_ZVSS AH11 P_ZVSS 1 2
R1 196_0402_1% R2 196_0402_1%
ME@ LOTES_ACA-ZIF-109-P12-A_FS1R2
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