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A B C D E
Compal Confidential
Model Name : VIUS3/S4
File Name : LA-8951PR01
1 1
BOM P/N:43
Compal Confidential
/
/x
su
2 2
VIUS3/S4 M/B Schematics Document
p.
om
Intel Ivy Bridge ULV Processor + Panther Point PCH
AMD Seymour XT
yc
m
//
3 2011-12-28 3
p:
REV:0.1
tt
h
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/24 2012/07/12 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 1 of 55
A B C D E
A B C D E
Compal confidential
File Name :VIUS3/VIUS4
Chief River
AMD Seymour XT Intel DDR3-SO-DIMM X1
1 23mm *23mm PCI-E X16 IVY Bridge SV/ULV BANK 0, 1
1
VRAM 128MB*16 Gen 2 (Sandy Bridge)
gDDR3*4 UP TO 1G Processor Dual Channel
BGA1023 DDR3-1066/1333(1.5V) for Sandy Bridge
DDR3-1600(1.5V) for Ivy Bridge
SATA3.0 HDD CONN
FDI *8 DMI2 *4
SATA3.0 HDD (SSD)
/
100MHz 100MHz
Std HDMI HDMI 1.4a 2.7GT/s 5GT/s
/x
Connector 6*SATA
(port0,1 Support SATA3)
su
2 2
PX 5.0
LVDS Intel 4*USB3.0
Connector
Panther Point
p.
14*USB2.0
PCI Express (Half) USB(WiMAX)
USB PORT 3.0 x1 (Left)
6*PCI-E x1
om
Mini card Slot 1 PCI-E(WLAN)
HM77/HM70
WLAN/WiMAX
USB PORT 2.0 x2 (Right)
FCBGA 989 Balls
IO Board
PCI Express (Full) 25mm*25mm
yc
mSATA(SSD) HD Audio
Mini card Slot 2 Card Reader RTS 5178 (2in1)
IO Board
SSD Gen 2
m
SPI ROM LPC BUS CMOS Camera
BIOS
// BlueTooth CONN
3 3
4MB*1
2MB*1 EC WLAN/WiMAX
p:
ENE KB9012
WWAN
LAN(10/100/Giga)
tt
WLAN/WiMAX
Realtek 2Channel Speaker
h
8105E-VD (10/100)
8111F-VL (Giga)
Int.KBD
Audio Codec Single Digital MIC
Touch Pad RealTek
RJ45 CONN ALC259-VC2
Audio Combo Jack
Sub-borad (APPLE type)
Thermal Sensor HeadPhone Output
4 Microphone Input 4
POWER BOARD EMC1403
IO Board
LED BOARD
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
IO Board THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 2 of 55
A B C D E
A B C D E
SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
1
+1.05VS_VTT S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+5VALW +1.5V +CPU_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +1.5V_IO +VCC_GFXCORE_AXG
+1.8VS BOARD ID Table Board ID / SKU ID Table for AD channel
State +0.75VS Vcc 3.3V +/- 5%
Board ID PCB Revision
Ra/Rc/Re 100K +/- 5%
0 0.1 Board ID Porject Phase
Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
1 G-series
0 0 0 V 0 V 0 V MP
2 G-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
3 G-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
4
/
G-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
S0
5 Y-series
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
6
/x
Y-series
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
7 Y-series
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PVT
S3 Y-series
O O O X 7 NC 2.500 V 3.300 V 3.300 V MP
su
2 2
S5 S4/AC
O O X X USB Port Table BOM Structure Table
3 External BTO Item BOM Structure
p.
S5 S4/ Battery only USB 3.0 USB 2.0 Port
O X X X USB Port INTEL UMA only UMA@
S5 S4/AC & Battery
xHCI1 0 GPU:Seymour XT PX@ PX5@
X X X X UHCI0
om
don't exist xHCI2 1 USB 3.0 Port (Left Side) HDMI HDMI@
Address xHCI3 2 Mini Card(WLAN) HDD1 (HM77 SATA 3.0) HDD1@
EC SM Bus1 address EC SM Bus2 address UHCI1
xHCI4 3 HDD2 (HM70 SATA 2.0) HDD2@
EHCI1
4 X (USB PORT disabled on HM70 ) Interna-Intel-USB3.0 IU3@
Device Device Address UHCI2
yc
Smart Battery 0001 011X b Thermal Sensor F75303M 1001_101xb
5 X (USB PORT disabled on HM70 ) Interna-Intel-USB2.0 IU2@
6 X (USB PORT disabled on HM70 ) Blue Tooth BT@
UHCI3
7 X (USB PORT disabled on HM70 ) 10/100 LAN 8105E@
PCH SM Bus address
m
8 USB/B (Right Side USB-BD) GIGA LAN 8111F@
UHCI4
9 USB/B (Right Side USB-BD) Connector ME@
Device Address
10 USB Port (Right Side CR-BD) 45 LEVEL 45@
DDR DIMM0 1001 000Xb
// EHCI2 UHCI5
11 Camera (LVDS) Unpop @
DDR DIMM2 1001 010Xb
3 3
12 X (USB PORT disabled on HM70 )
UHCI6
13 X (USB PORT disabled on HM70 )
AMD-GPU SM Bus address
p:
HM70 Disable xHCI3,xHCI4
Device Address
tt
Internal thermal sensor 1001 111Xb (0x9E)
SATA Port Table PCIe Port Table
h
elbaT lortnoC SUBMS HM77 HM70 HM77 HM70
SATA P0 GEN3/2/1 GEN3/2/1 SSD PCIe P1 Enable Enable LAN
lamrehT SATA P1 GEN3/2/1 Disable HDD (HM77) PCIe P2 Enable Enable WLAN
NALW
ECRUOS AGV TTAB NAWW MMIDOS 2109BK HCP rosneS SATA P2 GEN2/1 GEN2/1 HDD (HM70) PCIe P3 Enable Enable
SATA P3 GEN2/1 Disable PCIe P4 Enable Enable
1KC_CE_BMS
2109BK X V X X X X X SATA P4 GEN2/1 GEN2/1 PCIe P5 Enable Disable
1AD_CE_BMS WLAV3+ WLAV3+ SATA P5 GEN2/1 GEN2/1 PCIe P6 Enable Disable
2KC_CE_BMS Enable Disable
2109BK X X X X X X V PCIe P7
2AD_CE_BMS WLAV3+ SV3+ HM70 Disable P1,P3 Enable Disable
4 PCIe P8 4
KLCBMS
ATADBMS
HCP
WLAV3+
X X X V
SV3+
V
SV3+
X X HM70 Disable P5,P6,P7,P8
KLC0LMS
ATAD0LMS
HCP
WLAV3+
X X X X X X X
KLC1LMS
Security Classification Compal Secret Data Compal Electronics, Inc.
HCP V X V X X V X Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
ATAD1LMS WLAV3+ SV3+ SV3+ SV3+
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Friday, February 03, 2012 Sheet 3 of 55
A B C D E
5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PXS_RST# : Low -> Reset dGPU ; High ->Normal operation
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON
sequence, though a shorter ramp-up duration is preferred.
BACO option :
D D
2. VDDR3 should ramp-up before or simultaneously with VDDC. PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode)
PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
DPLL_PVDD, MPV18, and SPV18
ramp-up (or vice versa).)
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
/
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
/x
BIF_VDDC=VGA_CORE When GPU enable
BIF_VDDC=1.0V When BACO
VDDR1(1.5VGS) VDDR1 1.5V OFF OFF 2.8A
VDDC/VDDCI 1.12V OFF OFF 12.9A
su
C C
VDDC/VDDCI(1.12V)
p.
VDD_CT(1.8V)
PXS_RST# PE_EN BACO Switch
iGPU dGPU
om
PERSTb BIF_VDDC
PXS_PWREN
REFCLK PX_mode
yc
+3.3VALW MOS
+3.3VGS
Straps Reset 1
m
+1.5V SI4800
+1.5VGS
Straps Valid +1.0V +1.0VGS
Regulator
2 3
//
B
Global ASIC Reset B
+B Regulator
+VGA_CORE
+1.8V +1.8VGS
T4+16clock
SI4800
5 4
p:
PWRGOOD
tt
h
CPU part PCB part
ZZZ2 ZZZ1 ZZZ3 ZZZ4
UCPU1 CPU1@ UCPU1 CPU2@ UCPU1 CPU3@ UCPU1 CPU4@ ZZZ5
Hynix Hynix Hynix Hynix
I3_3217 1.8G I5_3427 1.8G I5_2557 1.4G 977_1.4G PCB 0R LA-8951P REV0 M/B S512@ H512@ S1G@ H1G@
SA00005L510 SA00005L900 SA00004VZ00 SA00005BJ40 DA60000TO00 X7641338L01 X7641338L02 X7641338L03 X7641338L04
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Thursday, February 02, 2012 Sheet 4 of 55
5 4 3 2 1
A B C D E
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
+1.05VS_VTT with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
R249 max length = 500 mils
24.9_0402_1%
- typical impedance = 14.5 mohms
UCPU1A
W=12mil L=500mil S=15mil
2
1 G3 PEG_COMP 1
PEG_ICOMPI G1
[15] DMI_CRX_PTX_N0 M2
DMI_RX#[0]
PEG_ICOMPO
PEG_RCOMPO
G4 Layout placement: Place close to U8 (GPU)
[15] DMI_CRX_PTX_N1 P6
P1 DMI_RX#[1]
[15] DMI_CRX_PTX_N2 DMI_RX#[2]
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