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A B C D E
1 1
2
Compal Confidential 2
Intel Haswell rPGA Processor with Lynx Point-H
Afterburn MXM
LA-9371P
3 3
2012-09-28
REV : 0.2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 1 of 53
A B C D E
A B C D E
Compal Confidential
Model Name : Afterburn
File Name : LA-9371P
1 1
DDR3-SO-DIMM2, 3
Ch B BANK 0, 1, 2, 3 Page 12
eDP MUX
eDP Panel Conn. PS8321 eDP
Page 22
Page 36 Intel DDR3-SO-DIMM0, 1
Ch A BANK 0, 1, 2, 3 Page 11
DPC eDPF Haswell DDR3L 1333MHz 1.35V
DP Switch
PI3VDP124 rPGA Processor
Page 36 MXM3.0 Conn
PEGx16 rPGA947
Dock Conn DPD NVidia: Port 1
Page 33 37.5mm*37.5mm Docking x 1
DPE Page 4,5,6,7,8,9,10 Page 33
Page 35
DP Conn CRT FDI x2 DMI x4 Port 2,5,6
USB conn x 3 (For I/O) daughter board
100MHz 100MHz
sub/B Page 6 CRT page 39
2 Dock Conn VGA Switch 2.7GT/s 5GT/s 2
ThunderBolt Page 33
2 to 2 Port 0,11
Mini DP Conn. Cactus Ridge Docking x 2
CRT MAX14885EETL CRT USB 3.0 x4
sub/B Page 4 sub/B Page 2,3,4 VGA Conn Page 33
daughter board Page 36 Page 36 Intel Port 1,4,5,9
USB 2.0 x 11 USB conn x 4(For I/O)
Port 3,4 X4 Lynx Point page 39
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz daughter board
PCH
Digital MIC Port 6
SATAx4 100MHz
695pin BGA Page 22
Expresscard
HD Audio HDA Codec sub/B Page 7
Port 8 Port 6 Port 5 Port 7 Port 1 Port 2 Port 4 Port 0 20mm*20mm
IDT 92HD91 Combo Jack Smart card Controller
(GEN1 1.5Gb/S Page 13,14,15,16,17,18,19,20,21 Page 26 Port 7
LS-9373P Page 4
GEN2 3Gb/S AU9540A51 Page 37
SPI
GEN3 6Gb/S)
daughter board SPK conn Port 8 FPR
LPC BUS
SATA HDD Page 27 Validity VFM471Page
Card Reader GLAN Intel WLAN ODD mSATA SATA HDD BIOS SPI ROM x1, 28
Realtek RTS5237 Clarkville Expresscard (MINI card) Conn. Conn. Conn. Conn. 16 MB
Page 16 Port 10
LS-9373P Page 4 Page 23 Page 23 (Secondary) (primary) Webcam
Page 29 sub/B Page 7 Page 25 Page 23 Page 23 Page 22
33MHz
3 Port 6 Port 13 Port 12
3
WWAN SIM Card
Lan Switch USB 2.0 Bus Page 25 Page 25
SD/MMC Slot
LS-9373P Page 4 PI3L500 Port 13
daughter board Page 29
WLAN
Dock Conn RJ45 Conn.
Page 33 Page 29
Super I/O TPM1.2
KBC EC ROM
Docking connector:
SMSC LPC47N217 Infineon SLB9656 2MB Page
Page 28
SMSC MES1132 SPI(PCH) 30
RJ45
Page 32
Accelerometer Page 30
ST HP3DC2 USB30*1
PS2
Page 28 USB20*1
DP*2
FAN conn. SMBus (PCH) Int.KBD Parallel port
Page 24 Touch Pad
Page 38 Page 38 Serial port
4 PS/2 4
RTC CKT. Page 13 Line in/Line out
SATAx2
Power On/Off CKT. VGA
LS-9376P Page 4
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/06/11 2013/06/11 Title
DC/DC interface CKT.
Page 34
Issued Date Deciphered Date
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 2 of 53
A B C D E
5 4 3 2 1
( O MEANS ON X MEANS OFF )
Voltage Rails Symbol Note :
+RTCVCC B+ +5VDS +1.35V +5VS
+3VDS +0.675VS +3VS
D
+1.5VS : means Digital Ground D
power
plane +VCC_CORE
+1.05VS
+1.05VM : means Analog Ground
@ : means just reserve , no build
State AMT@ : means just install for support iAMT
CONN@ : means ME part.
L Layout Notes
07/24 update
S0
O O O O O : Question Area Mark.(Wait check)
S1
C
O O O O O C
S3
O O O O X Install below 45 level BOM structure for ver. 0.1
S5 S4/AC 45@ : means just put it in the BOM of 45 level.
O O O X X
S5 S4/ Battery only
O O X X X
S5 S4/AC & Battery
don't exist
O X X X X Install below 43 level BOM structure for ver. 0.1
DEBUG@ : means just build when PCIE port 80 CARD function enable.Remove before MP
SMBUS Control Table
2nd
SOURCE BATT XDP SODIMM G-SENSOR TP NIC NFC EC MXM
BATT
B I2C_MAIN_CLK
I2C_MAIN_DAT
SMSC1126
V X X X X X X X X X B
I2C_BAY_CLK
I2C_BAY_DAT
SMSC1126
X V X X X X X X X X
MEM_SMBCLK
MEM_SMBDATA
Haswell
X X V V V V X X X X
LAN_SMBCLK
LAN_SMBDATA
Haswell
X X X X X X V V X X
SML1_SMBCLK
SML1_SMBDATA Haswell
X X X X X X X X V V
Stapping Options Flash
GPIO 51 GPIO 19 Boot BIOS Destination
Bit 1 Bit 0
A
0 0 Reserved A
0 1 RSVD
1 0 SPI
1 1 LPC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 3 of 53
5 4 3 2 1
5 4 3 2 1
+VCCIOA_OUT
PEG_COMP 2 1
D 24.9_0402_1% RC1 D
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
PEG_CRX_GTX_P[0..15]
Haswell rPGA EDS PEG_CRX_GTX_P[0..15] <35>
JCPU1A CONN@
PEG_CRX_GTX_N[0..15]
PEG_CRX_GTX_N[0..15] <35>
E23 PEG_COMP
PEG_RCOMP M29 PEG_CRX_GTX_N0 PEG_CTX_GRX_P[0..15]
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28 PEG_CRX_GTX_N1 PEG_CTX_GRX_P[0..15] <35>
<14> DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1
DMI_CRX_PTX_N1 C21 M31 PEG_CRX_GTX_N2 PEG_CTX_GRX_N[0..15]
<14> DMI_CRX_PTX_N1 DMI_RXN_1 PEG_RXN_2 PEG_CTX_GRX_N[0..15] <35>
DMI_CRX_PTX_N2 B21 L30 PEG_CRX_GTX_N3
<14> DMI_CRX_PTX_N2 DMI_RXN_2 PEG_RXN_3
DMI_CRX_PTX_N3 A21 M33 PEG_CRX_GTX_N4
<14> DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PEG_CRX_GTX_N5
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35 PEG_CRX_GTX_N6
<14> DMI_CRX_PTX_P0
PEG
DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34 PEG_CRX_GTX_N7
<14> DMI_CRX_PTX_P1 DMI_RXP_1 PEG_RXN_7
DMI_CRX_PTX_P2 B20 E29 PEG_CRX_GTX_N8
<14> DMI_CRX_PTX_P2 DMI_RXP_2 PEG_RXN_8
DMI_CRX_PTX_P3 A20 D28 PEG_CRX_GTX_N9
<14> DMI_CRX_PTX_P3
DMI
DMI
DMI_RXP_3 PEG_RXN_9 E31 PEG_CRX_GTX_N10
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30 PEG_CRX_GTX_N11
<14> DMI_CTX_PRX_N0 C17 DMI_TXN_0 PEG_RXN_11 E35 2 1 0.22U_0402_6.3V6K
DMI_CTX_PRX_N1 PEG_CRX_GTX_N12 PEG_CTX_GRX_C_P0 CC1 PEG_CTX_GRX_P0
<14> DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34 PEG_CRX_GTX_N13 PEG_CTX_GRX_C_N0 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N0
CC2
<14> DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 A17 DMI_TXN_2 PEG_RXN_13 E33 PEG_CRX_GTX_N14
<14> DMI_CTX_PRX_N3 DMI_TXN_3 PEG_RXN_14 E32 PEG_CRX_GTX_N15 PEG_CTX_GRX_C_P1 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P1
CC3
DMI_CTX_PRX_P0 D17 PEG_RXN_15 L29 PEG_CRX_GTX_P0 PEG_CTX_GRX_C_N1 CC4 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N1
<14> DMI_CTX_PRX_P0 C18 DMI_TXP_0 PEG_RXP_0 L28
DMI_CTX_PRX_P1 PEG_CRX_GTX_P1
<14> DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 B18 DMI_TXP_1 PEG_RXP_1 L31 PEG_CRX_GTX_P2 PEG_CTX_GRX_C_P2 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P2
CC5
C <14> DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 A18 DMI_TXP_2 PEG_RXP_2 K30 PEG_CRX_GTX_P3 PEG_CTX_GRX_C_N2 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N2 C
CC6
<14> DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33 PEG_CRX_GTX_P4
PEG_RXP_4 K32 PEG_CRX_GTX_P5 PEG_CTX_GRX_C_P3 CC7 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P3
PEG_RXP_5 L35 PEG_CRX_GTX_P6 PEG_CTX_GRX_C_N3 CC8 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N3
PEG_RXP_6 K34 PEG_CRX_GTX_P7
PEG_RXP_7 F29 PEG_CRX_GTX_P8 PEG_CTX_GRX_C_P4 CC9 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P4
FDI_CSYNC H29 PEG_RXP_8 E28 PEG_CRX_GTX_P9 PEG_CTX_GRX_C_N4 CC10 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N4
<14> FDI_CSYNC
FDI
FDI
FDI_INT J29 FDI_CSYNC PEG_RXP_9 F31 PEG_CRX_GTX_P10
<14> FDI_INT DISP_INT PEG_RXP_10 E30 PEG_CRX_GTX_P11 PEG_CTX_GRX_C_P5 CC11 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P5
PEG_RXP_11 F35 PEG_CRX_GTX_P12 PEG_CTX_GRX_C_N5 CC12 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N5
PEG_RXP_12 E34 PEG_CRX_GTX_P13
PEG_RXP_13 F33 PEG_CRX_GTX_P14 PEG_CTX_GRX_C_P6 CC13 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P6
PEG_RXP_14 D32 PEG_CRX_GTX_P15 PEG_CTX_GRX_C_N6 CC14 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N6
PEG_RXP_15 H35 PEG_CTX_GRX_C_N0
PEG_TXN_0 H34 PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_P7 CC15 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P7
PEG_TXN_1 J33 PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_N7 CC16 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N7
PEG_TXN_2 H32 PEG_CTX_GRX_C_N3
PEG_TXN_3 J31 PEG_CTX_GRX_C_N4 PEG_CTX_GRX_C_P8 CC17 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P8
PEG_TXN_4 G30 PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_N8 CC18 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N8
PEG_TXN_5 C33 PEG_CTX_GRX_C_N6
PEG_TXN_6 B32 PEG_CTX_GRX_C_N7 PEG_CTX_GRX_C_P9 CC19 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P9
PEG_TXN_7 B31 PEG_CTX_GRX_C_N8 PEG_CTX_GRX_C_N9 CC20 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N9
PEG_TXN_8 A30 PEG_CTX_GRX_C_N9
PEG_TXN_9 B29 PEG_CTX_GRX_C_N10 PEG_CTX_GRX_C_P10 CC21 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P10
PEG_TXN_10 A28 PEG_CTX_GRX_C_N11 PEG_CTX_GRX_C_N10 CC22 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N10
PEG_TXN_11 B27 PEG_CTX_GRX_C_N12
PEG_TXN_12 A26 PEG_CTX_GRX_C_N13 PEG_CTX_GRX_C_P11 CC23 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P11
PEG_TXN_13 B25 PEG_CTX_GRX_C_N14 PEG_CTX_GRX_C_N11 CC24 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N11
PEG_TXN_14 A24 PEG_CTX_GRX_C_N15
PEG_TXN_15 J35 PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P12 CC25 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P12
PEG_TXP_0 G34 PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N12 CC26 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N12
PEG_TXP_1 H33 PEG_CTX_GRX_C_P2
B PEG_TXP_2 G32 PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P13 CC27 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P13 B
PEG_TXP_3 H31 PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N13 CC28 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N13
PEG_TXP_4 H30 PEG_CTX_GRX_C_P5
PEG_TXP_5 B33 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P14 CC29 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P14
PEG_TXP_6 A32 PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N14 CC30 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N14
PEG_TXP_7 C31 PEG_CTX_GRX_C_P8
PEG_TXP_8 B30 PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P15 CC31 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P15
PEG_TXP_9 C29 PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_N15 CC32 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N15
PEG_TXP_10 B28 PEG_CTX_GRX_C_P11
PEG_TXP_11 C27 PEG_CTX_GRX_C_P12
PEG_TXP_12 B26 PEG_CTX_GRX_C_P13
PEG_TXP_13 C25 PEG_CTX_GRX_C_P14
PEG_TXP_14 B24 PEG_CTX_GRX_C_P15
PEG_TXP_15
1 OF 9
INTEL_HASWELL_HASWELL
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DMI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 4 of 53
5 4 3 2 1
5 4 3 2 1
+VCCIO_OUT
SM_DRAMPWROK with DDR Power Gating Topology
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
+VCCIO_OUT +VCCIO_OUT
CC33
CC34
+1.35VS
+5VDS 2 2 JXDP1
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