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COMPAL CONFIDENTIAL
MODEL NAME : 888L2(SOLANO2-M)
Date: 01/11/01
Version: 2.0
Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cover Sheet
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 1 of 42
MODEL NAME : 888L2 (SOLANO2-M)
UPGA2 Decoupling
Socket CapacitorS
PAGE 4,5,6 PAGE 6
FSB BUS
PAGE 13
PAGE 12
CRT CONN. GMCH2-M
IDSEL: AD11
LVDS DVO/Vlink HOST-HUB BRIDGE
LCD/INV. CONN. VCH PAGE 12 IDSEL: AD13 MEMORY BUS SODIMM 0 CLOCK
INTERNAL GFX SODIMM 1 CIRCUIT
DISPLAY CACHE CONN. & ITP PAGE 13 PAGE 7,8,9 PAGE 10
PCI BUS HUB_ILNK
PAGE 11
CARD-BUS MINI_PCI CONN ICH2-M HDD CONN.
CONTROLLER
OZ 6933T MODEM/LAN
AC_LINK1/LAN BUS#0, DEV#30, DEV#31: PAGE 17
DC/DC
IDSEL: AD19 IDSEL: AD27, AD28 HUB, LPC, IDE, USB, SMBUS, CIRCUIT
AC'97 SECOND MODULE
PIRQA#, PIRQC# PAGE 19 PIRQB#, PIRQD# PAGE 29
BUS#1, DEV#8:
CONN. PAGE 17
INTERNAL LAN CONTROLLER
PAGE 14,15,16
CD-ROM
PCCARD CARDBUS CONN. PAGE 17
POWER RJ11 RJ45
SLOT 1/2 PAGE 30-34
PAGE 20 PAGE 20 Sub board USB CONN.
PAGE 18
FWH
PAGE 14 AC_LINK0 AMP & AC97
CODECPAGE 27
LPC BUS
KB BIOS NS PC87393
PAGE 22
NS PC87570EXT X Bus Head
RTC BATT & LPC-TO-X Bus Line in Mic
Phone
ON/OFF BTN KBD & S/IO
PAGE 25 PAGE 28 PAGE 28 PAGE 28
INT KBD PAGE 22 PAGE 21
PAGE 23
PS/2 T-PAD SUSP N
ED
KYOR &
EB AD O N
C N . C T
K SIO PIO FDD.
M UEON
O S C N.
PAGE 25 PAGE 23 PAGE 26 PAGE 24 PAGE 24 PAGE 17
Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D System Block Diagram
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 2 of 42
Revision History
# Date Description Version
1 2000/7/21 First Release (EVT-SST) 0.1
2 2000/9/20 Second Release (DVT1-PT1) 0.2A
3 2000/11/3 Third Release (DVT2-PT2) 0.2C1
4 2000/12/27 Fouth Release (ST) 1B
5 2001/01/11 fifth release (QT) 2.0
Chip information EVT (SST)
GMCH2-M QA38ES (A0)
GMCH2-M FW82815EM
ICH2-M Q967ES (B0)
Version S-spec. Q-spec. VCH Q989ES (A0)
A0 QA38 DVT1 (PT1) DVT2 (PT2)
GMCH2-M QA75ES (A1)
A1 SL4MP QA75
ICH2-M QA57ES (B2)
VCH Q076ES (A1)
ICH2-M FW82801BAM
ST
Version S-spec. Q-spec. GMCH2-M A1
ICH2-M B2
A0 Q908, Q909, Q910, Q911, Q912
VCH A2
B0 SL45HQ Q967, Q968 QT same as ST
B1 SL4HN QA36, QA37
B2 QA56, QA57
VCH FW82807AA
Version S-spec. Q-spec.
A0 Q989
A1 QA76
A2 QB41ES
Compal Electronics, Inc.
Title
Revision History
Size Document Number Rev
2.0
888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 3 of 42
A B C D E
HA#[3..31] HD[0..63]
<7> HA#[3..31] HD#[0..63] <7>
CPU_VID[0..4]
U5A CPU_VID[0..4] <5>
HA#3 L3 D10 HD#0 RP40 +3VS +3VS RP41
HA#4 K3 A3# D0# D11 HD#1 8P4R-10K 8P4R-1K
HA#5 J2 A4# COPPERMINE D1# C7 HD#2 1 8 1 8 CPU_VID0
HA#6 L4 A5# D2# C8 HD#3 2 7 2 7 CPU_VID1
HA#7 L1 A6# D3# B9 HD#4 3 6 3 6 CPU_VID2
HA#8 K5 A7# D4# A9 HD#5 4 5 4 5 CPU_VID3
HA#9 K1 A8# D5# C10 HD#6
HA#10 J1 A9# D6# B11 HD#7 1 2 CPU_VID4
HA#11 J3 A10# D7# C12 HD#8 1 2 R20 1K
+CPU_IO A11# D8# +3VS
HA#12 K4 B13 HD#9 R30 @10K
4 4
HA#13 G1 A12# D9# A14 HD#10 VCH_VID[0..4]
A13# D10# VCH_VID[0..4] <12>
R243 1 2 56.2_1% CPURST# HA#14 H1 B12 HD#11 VID[0..4]
A14# D11# VID[0..4] <30>
HA#15 E4 E12 HD#12
R42 1 2 1.5K FLUSH# HA#16 F1 A15# D12# B16 HD#13 U4
HA#17 F4 A16# D13# A13 HD#14 CPU_VID0 3 2 VID0
R107 1 2 150 PICD0_CPU HA#18 F2 A17# D14# D13 HD#15 CPU_VID1 7 A0 C0 6 VID1
HA#19 E1 A18# D15# D15 HD#16 CPU_VID2 11 A1 C1 10 VID2
R106 1 2 150 PICD1_CPU HA#20 C4 A19# D16# D12 HD#17 CPU_VID3 17 A2 C2 16 VID3
HA#21 D3 A20# D17# B14 HD#18 RP42 CPU_VID4 21 A3 C3 20 VID4
R44 1.5K FERR# HA#22 A21# D18# HD#19 8P4R-0 A4 C4
2 1 D1 E14
HA#23 E2 A22# D19# C13 HD#20 VCH_VID0 1 8 R_VID0 4 5
R293 2 1 1.5K RCPUSLP# HA#24 D5 A23# D20# A19 HD#21 VCH_VID1 2 7 R_VID1 8 B0 D0 9
HA#25 D4 A24# D21# B17 HD#22 VCH_VID2 3 6 R_VID2 14 B1 D1 15
HA#26 C3 A25# D22# A18 HD#23 VCH_VID3 4 5 R_VID3 18 B2 D2 19
HA#27 C1 A26# REQUEST DATA D23# C17 HD#24 VCH_VID4 1 2 R_VID4 22 B3 D3 23
HA#28 B3 A27# D24# D17 HD#25 R429 B4 D4
PHASE PHASE
HA#29 A3 A28# D25# C18 HD#26 @0_0402 1 24
A29# SIGNALS SIGNALS D26# BE# VCC +5VS
HA#30 B2 B19 HD#27
1
HA#31 C2 A30# D27# D18 HD#28 13 12 C22
A31# D28# HD#29 BX GND
A4 B20
A5 A32# D29# A20 HD#30 SN74CBT3383 .1UF
2
2
2
2
2
A33# D30#
2
B4 B21 HD#31
C5 A34# D31# D19 HD#32 R19 R24
A35# D32# C21 HD#33 1K_0402 1K_0402
T2 D33# E18 HD#34
<7> HREQ#0 REQ0# D34#
V4 C20 HD#35 VR_HI/LO#
<7> HREQ#1 REQ1# D35# VR_HI/LO# <15,30>
1
1
1
1
1
V2 F19 HD#36
+CPU_IO <7> HREQ#2 REQ2# D36#
W3 D20 HD#37
<7> HREQ#3 REQ3# D37#
W5 D21 HD#38 R18 R27
<7> HREQ#4 REQ4# D38#
VID[4:0] CPU VCC VID[4:0] CPU VCC
3 3
W2 H18 HD#39 @1K_0402 R22 1K_0402
2
RP# D39# F18 HD#40 1K_0402
R26 AB2 D40# J18 HD#41
<7> ADS# ADS# D41#
10K_0402
D42#
F21
E20
HD#42
HD#43
00000 2.00 10000 1.275
D43#
BSEL0 AA1
AERR# D44#
H19 HD#44
00001 1.95 10001 1.250
1
AB1 ERROR E21 HD#45
AP0# D45#
Y2
E6 AP1#
SIGNALS
D46#
J20
H21
HD#46
HD#47
00010 1.90 10010 1.225
BERR# D47#
V21
BINIT# D48#
L18 HD#48
HD#49
00011 1.85 10011 1.200
AD9 G20
IERR# D49#
+CPU_IO 10_0402 2 1 R217 C6 D50#
P18
G21
HD#50
HD#51
00100 1.80 10100 1.175
BREQ0# D51#
<7> BPRI#
U4
T4 BPRI# ARBITRATION D52#
K18
K21
HD#52
HD#53
00101 1.75 10101 1.150
<7> BNR#
2
BNR# D53#
R105
<7> HLOCK#
R1
LOCK#
PHASE
D54#
M18
L21
HD#54
HD#55
* 900MHZ 00110 1.70 10110 1.125
SIGNALS D55#
@10K_0402
V1 D56#
R19
K19
HD#56
HD#57
00111 1.65 10111 1.100
<7> HIT# HIT# D57#
<7> HITM#
Y4
HITM#
SNOOP PHASE
D58#
T20 HD#58
* 850MHZ 01000 1.60 11000 1.075
1
BSEL1 U3 SIGNALS J21 HD#59
<7> DEFER# DEFER# D59#
AA21 D60#
L20
M19
HD#60
HD#61
01001 1.55 11001 1.050
1
BP2# D61#
R104
Y21
W21 BP3#
RESPONSE
D62#
U18
R18
HD#62
HD#63
01010 1.50 11010 1.025
PHASE
BPM0# D63#
100_0402 W19
U2 BPM1# SIGNALS 01011 1.45 11011 1.000
<7> HTRDY# TRDY#
<7> RS#0
U1
RS0# DEP0#
V20
01100 1.40 11100 0.975
2
AA2 T21
<7> RS#1 RS1# DEP1#
2
<7> RS#2
W1
RS2# DEP2#
U21
* 01101 1.35 11101 0.950 2
Y1 R21
RSP# DEP3#
AD10 DEP4#
V18
P21
01110 1.30 11110 0.925
<14> A20M# A20M# DEP5#
<14> FERR#
FERR# AC12
AC13 FERR#
PC
DEP6#
P20
U19
01111 NO CPU 11111 NO CPU
<14> IGNNE# C O MPATIBILITY
V5 IGNNE# DEP7#
<14> CPU_PWRGD PWRGOOD SIGNALS
AB10 AA3
<14> SMI# SMI# DBSY# DBSY# <7> +3VS
2 1 T1
+2_5V_CLK DRDY# DRDY# <7>
R210 1.5K ITP_TDO AC15
RP32 1 8 8P4R-1.5K ITP_TDI AD13 TDO DIAGNOSTIC
ITP_TMS TDI
2 7 AD14 & TEST 2 1 1 2
+CPU_IO 3 6 ITP_TRST# AA14 TMS R102 @33_0402 C97 @15PF 1 2
SIGNALS
2
4 5 ITP_TCK AA11 TRST# R245 10K_0402
R100 2 1 1.5K ITP_PREQ# AB20 TCK AA18 C310
15
C L K_APIC_CPU <11>
2
R101 2 1 56.2_1% GTL_PRDY# W20 PREQ# PICCLK Y20 PICD1_CPU R103 2 1 0_0402 PICD1 MAX1617A U20
PRDY# PICD1 PICD1 <14> .1UF
1
BSEL0 AA12 AB21 PICD0_CPU R99 2 1 0_0402 PICD0 16
STBY#
VCC
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