Service Manuals, User Guides, Schematic Diagrams or docs for : Compal Laptop LA-9351p r0.1 compal_la-9351p_r0.1_schematics
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5 4 3 2 1
D D
C C
B B
Intel Ivy Bridge/Panther Point
AMD Seymour XT
2012-05-08 Rev 0.1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 1 of 50
5 4 3 2 1
5 4 3 2 1
Compal Confidential
Model Name : VBL30/31 Fan CONN
page 38
File Name :LA-9351P PCI-E X16 Mobile IVY Bridge
CPU Dual / Quad Core
D Memory BUS(DDRIII) D
AMD Seymour XT Socket-rPGA989 Dual Channel 204pin DDRIII-SO-DIMM X2
1.5V DDRIII 1066/1333 BANK 0, 1, 2, 3 page 11,12
37.5mm*37.5mm page 5~10
23mm *23mm
VRAM DMI X4 FDI x8
page 13~18
page 27
USB20
CRT
page 28
Intel
LCD Conn. Panther Point USB/B Right Int. Camera RTS5129 3IN1
page 32 page 28 page 33
page 29
C
HDMI Conn. 989pin FCBGA C
USB30 USB 3.0 conn
page 33
SPI ROM SATA port
page 37
SATA HDD SATA ODD
PCIE 2.5GT/s) 100MHz page 30 page 30
page 19~26
port 2 port 1 HD Audio 3.3V 24.576MHz/48Mhz
PCIeMini Card RTL8111GS LPC BUS
WLAN & BT 2.0 33MHz HDA Codec
PCIe port 1 ALC259
page 34
USB port 8 page 31 ENE KB9012
PCIe port 2
page 36
page 32
B B
RJ45
Int. MIC
page 31 MIC CONN HP CONN SPK CONN
USB&Audio/B Touch Pad Int.KBD page 34 page 32 page 32 page 34
page 32 page 38 page 35
Power/B
page 38
Touch Pad/B
page 38
RTC CKT.
page 30
A
DC/DC Interface CKT. A
page 39
Security Classification Compal Secret Data Compal Electronics, Inc.
Power Circuit DC/DC Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
page 40~50 Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 2 of 50
5 4 3 2 1
5 4 3 2 1
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW
B+
SUSP
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
SUSP#
DESIGN CURRENT 2A +1.8VS
SY8033BDBC
D D
RT8205
Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800
VGA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
PCIE_OK
DESIGN CURRENT 100mA +3VS_DELAY
C C
P-CHANNEL
AO-3413
VR_ON
DESIGN CURRENT 52A +CPU_CORE
NCP6132AMNR2G
DESIGN CURRENT 30A +GFX_CORE
DGPU_PWR_EN / SUSP#
DESIGN CURRENT 26A +VGA_CORE
APL5912
SUSP#
Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 18A +1.05VS_VCCP
TPS51212DSCR
B B
SYSON
Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 15A +1.5V +1.5V_CPU
RT8209BGQW
CPU1.5V_S3_GATE / SUSP
DESIGN CURRENT 2A +0.75VS
RT8207MZQW
SUSP
DESIGN CURRENT 12A +1.5VS
SI4856ADY
SUSP#
DESIGN CURRENT 6A +VCCSA
A A
RT8209BGQW
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1
Voltage Rails
EC SM Bus1 address EC SM Bus2 address
+5VS
+3VS Power Device Address Power Device Address
power
+1.5VS +3VALW Smart Battery 0001 011x b +3VS VGA Internal thermal sensor 1001 111Xb (0x9E)
plane
+1.05VS_VTT
D D
+5VALW +1.5V +CPU_CORE
+B +VGA_CORE
+3VALW +1.5V_IO +VCC_GFXCORE_AXG
PCH SM Bus address
+1.8VS
State +0.75VS Power Device Address
+3VS DDR DIMMA 1001 000x b
+3VS DDR DIMMB 1001 010x b
S0
O O O O SMBUS Control Table
Thermal
WLAN Sensor
S3
O O O SOURCE VGA BATT KB9012 SODIMM PCH
C X WWAN C
SMB_EC_CK1
S5 S4/AC
O O X X SMB_EC_DA1
KB9012 X V X X X X X
+3VALW +3VALW
SMB_EC_CK2
S5 S4/ Battery only
O X X X SMB_EC_DA2
KB9012 X X X X X X V
+3VS
+3VALW
SMBCLK
S5 S4/AC & Battery
X X X X SMBDATA
PCH X X X V
+3VS
V
+3VS
X X
don't exist +3VALW
SML0CLK
SIGNAL SML0DATA
PCH X X X X X X X
+3VALW
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
SML1CLK
Full ON HIGH HIGH HIGH HIGH ON ON ON ON SML1DATA
PCH V
+3VS
X V
+3VS
X X +3VS
V X
+3VALW
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF B
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
PCH X76 and PCBA table
config
ZZZ X76@ ZZZ @ R359 @ R361 @ R462 @
HYN 1G HYN 1G 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76
ZZZ X76@ ZZZ @ R360 @ R361 @ R461 @
SAM 1G SAM 1G 10K_0402_5% 10K_0402_5% 10K_0402_5%
UH1
BD82HM70 QPXH C1 BGA 989P
PCH PCH@
ZZZ DAZ@ ZZZ DA8@ ZZZ DA4@ ZZZ DA2@
PCB
A PCB LA-6732P REV10 PCB LA-9351P REV01 PCB LS-6732P REV10 PCB LS-6731P REV10 A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 4 of 50
5 4 3 2 1
5 4 3 2 1
+1.05VS_VCCP
JCPU1I
RC2 PEG_ICOMPI and RCOMPO signals should be shorted and routed
24.9_0402_1% with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils T35 F22
JCPU1A - typical impedance = 14.5 mohms T34 VSS161 VSS234 F19
D J22 PEG_COMP T33 VSS162 VSS235 E30 D
PEG_ICOMPI J21 T32 VSS163 VSS236 E27
B27 PEG_ICOMPO H22 T31 VSS164 VSS237 E24
<21> DMI_PTX_CRX_N0 DMI_RX#[0] PEG_RCOMPO VSS165 VSS238
<21> DMI_PTX_CRX_N1 B25 T30 E21
A25 DMI_RX#[1] T29 VSS166 VSS239 E18
<21> DMI_PTX_CRX_N2 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] <13> VSS167 VSS240
<21> DMI_PTX_CRX_N3 B24 K33 PCIE_GTX_C_CRX_N0 T28 E15
DMI_RX#[3] PEG_RX#[0] M35 PCIE_GTX_C_CRX_N1 T27 VSS168 VSS241 E13
B28 PEG_RX#[1] L34 PCIE_GTX_C_CRX_N2 T26 VSS169 VSS242 E10
<21> DMI_PTX_CRX_P0 DMI_RX[0] PEG_RX#[2] VSS170 VSS243
<21> DMI_PTX_CRX_P1 B26 J35 PCIE_GTX_C_CRX_N3 P9 E9
A24 DMI_RX[1] PEG_RX#[3] J32 PCIE_GTX_C_CRX_N4 P8 VSS171 VSS244 E8
<21> DMI_PTX_CRX_P2
DMI
B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_GTX_C_CRX_N5 P6 VSS172 VSS245 E7
<21> DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5] VSS173 VSS246
H31 PCIE_GTX_C_CRX_N6 P5 E6
G21 PEG_RX#[6] G33 PCIE_GTX_C_CRX_N7 P3 VSS174 VSS247 E5
<21> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] VSS175 VSS248
E22 G30 PCIE_GTX_C_CRX_N8 P2 E4
<21> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] VSS176 VSS249
F21 F35 PCIE_GTX_C_CRX_N9 N35 E3
<21> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] VSS177 VSS250
D21 E34 PCIE_GTX_C_CRX_N10 N34 E2
<21> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] VSS178 VSS251
E32 PCIE_GTX_C_CRX_N11 N33 E1
G22 PEG_RX#[11] D33 PCIE_GTX_C_CRX_N12 N32 VSS179 VSS252 D35
<21> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] VSS180 VSS253
D22 D31 PCIE_GTX_C_CRX_N13 N31 D32
<21> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] VSS181 VSS254
F20 B33 PCIE_GTX_C_CRX_N14 N30 D29
PCI EXPRESS* - GRAPHICS
<21> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] VSS182 VSS255
C21 C32 PCIE_GTX_C_CRX_N15 N29 D26
<21> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] VSS183 VSS256
N28 D20
PCIE_GTX_C_CRX_P[0..15] <13> VSS184 VSS257
J33 PCIE_GTX_C_CRX_P0 N27 D17
PEG_RX[0] L35 PCIE_GTX_C_CRX_P1 N26 VSS185 VSS258 C34
PEG_RX[1] K34 PCIE_GTX_C_CRX_P2 M34 VSS186 VSS259 C31
A21 PEG_RX[2] H35 PCIE_GTX_C_CRX_P3 L33 VSS187 VSS260 C28
<21> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3] VSS188 VSS261
H19 H32 PCIE_GTX_C_CRX_P4 L30 C27
<21> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] VSS189 VSS262
E19 G34 PCIE_GTX_C_CRX_P5 L27 C25
<21> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] VSS190 VSS263
F18 G31 PCIE_GTX_C_CRX_P6 L9 C23
<21> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] VSS191 VSS264
Intel(R) FDI
B21 F33 PCIE_GTX_C_CRX_P7 L8 C10
<21> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7] VSS192 VSS265
C20 F30 PCIE_GTX_C_CRX_P8 L6 C1
<21> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] VSS193 VSS266
D18 E35 PCIE_GTX_C_CRX_P9 L5 B22
C <21> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] VSS194 VSS267 C
E17 E33 PCIE_GTX_C_CRX_P10 L4 B19
<21> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
F32
D34
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
A22 E31 PCIE_GTX_C_CRX_P13 L1 B13
<21> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] VSS198 VSS271
G19 C33 PCIE_GTX_C_CRX_P14 K35 B11
<21> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14] VSS199 VSS272
E20 B32 PCIE_GTX_C_CRX_P15 K32 B9
<21> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15] VSS200 VSS273
G18 K29 B8
<21> FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_C_GRX_N[0..15] <13> VSS201 VSS274
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