Service Manuals, User Guides, Schematic Diagrams or docs for : Compaq-HP DV6 DV7 LX6
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1 2 3 4 5 6 7 8
PCB STACK UP
LX6/7 (Liverpool) BLOCK DIAGRAM 01
6L Dis.
VRAM DDR3*8
DDR3 800,1066,1333 MT/s (512Mb,1Gb,2Gb)
LAYER 1 : TOP DDR3-SODIMM1
A
LAYER 2 : SGND PAGE 12
Intel Clarksfield PAGE 19-20 A
LAYER 3 : IN1(High) Arrandale HDMI CON HDMI
LAYER 4 : IN2(Low) HDMI (1920*1200)
DDR3 800,1066,1333 MT/s ATI Park XT
LAYER 5 : SVCC
DDR3-SODIMM2 CPU 45Watt PAGE 31
PCI-Express (64bit)
LAYER 6 : BOT PAGE 13 35Watt Gen2 X 16
Madison Pro
4 Core (128bit)
( rPGA 989 ) (FCBGA) CRT CRT PAGE 23
962p 29X29mm LVDS Mux
PAGE 3-6
PAGE 14-18 LCD CONN for
PAGE 21
BCLK133M 32.768KHz dual channel
DMI*4 DMI100M 27MHz
(15.6",17")
DP120M 14.318MHz
PAGE 22 HDMI
SATA0 300MB/s 100M PCIE Dual Channel LVDS
SATA - 1st HDD
133M BCLK
Level
PAGE 30 PCH 3.5Watt CLOCK GEN Shifter
100M PCIE
B B
SATA0 300MB/s 96M DOT 9LRS3197 USB2.0 Port X2 USB2.0 Port PAGE 31
SATA - 2nd HDD Platform REF CLK POWER LED POWER LED
PAGE 30 PAGE 02
Controller HDD LED HDD LED
SATA0 300MB/s Hub CRT Form 17" Form 15"
SATA - CD-ROM LVDS PAGE 28 PAGE 28
PAGE 30 PAGE 7-11 iGPU HDMI 8,9 7
USB2.0 48M
E-SATA/USB Port (1)
SATA0 300MB/s
2 0 6 4 10 12 11 3
PAGE 28
Fingerprint USB2.0 Port BlueTooth Webcam w/ Mic USB2.0 Port Touchscreen
PAGE 28 PAGE 28 PAGE 28 PAGE 22 Card Reader Form 15" PAGE 28
Accelerometer SMBUS
PCI-E 100M PAGE 28
HP302DLTR8 Realtek
DDR III SMDDR_VTERM and PAGE 26 RTS5159
GPU+1.5V/+1.0V(RT8207G) Azalia
X1 X1
PAGE 40 PAGE 24
SPI ROM half size
PAGE 7 LAN mini-card
C
BATTERY SELECTOR LPC Realtek (Wireless LAN C
5-in-1
PAGE 42 Audio PCIE-LAN Shirley Peak flash media
RTL8111(D) 802.11a/b/g/n) slot(SD/MS/MMC/
IDT92HD80 GigaLAN
XD/MSP)
PAGE 33
SYSTEM CHARGER(P2806) PAGE 25 PAGE 29 PAGE 24
PAGE 41 32.768KHz
25MHz
SYSTEM POWER RT8206B Keyboard Touch Pad
PAGE 35 Light Sensor
PAGE 32 ENE KBC RJ45
Amplifier PAGE 29
+1.05V_VTT and GPU
+1.8V/+3V(VT358) GMT G9931P1U KB3926 D2 TPA3111D1
SYSTEM FAN
PAGE 38 PAGE 27
PAGE 33 PAGE 32
VCCP +1.05V/+1.8V(RT8204)
BIOS
PAGE 36 (SYSTEM BIOS)
D
PAGE 32 D
VGACORE/VDDCI(RT8208/RT9018A) Audio Jack Jack to Jack to
PAGE 39
DMIC (Headphone/MIC) Speaker Sub-Woofer
PAGE 22 PAGE 26 PAGE 25 PAGE 27 PROJECT : LX6_LX7
Quanta Computer Inc.
CPU CORE (ADP3212)
Size Document Number Rev
PAGE 37 Custom 1A
NB5 BLOCK DIAGRAM
Date: Tuesday, February 02, 2010 Sheet 1 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
25mA 150mA 150mA
02
+3V +VDDCORE_CLK Y2
+1.05V +VDDIO_CLK +3V +VDDSE_CLK L19 XTAL_IN 1 2XTAL_OUT +3V
L20 L22 1 2 C325 4.7U/6.3V_6
1 2 C322 0.1U/10V_4 1 2 C389 4.7U/6.3V_6 HCB1608KF-181T15_6
1
1
HCB1608KF-181T15_6 C342 0.1U/10V_4 HCB1608KF-181T15_6 C375 0.1U/10V_4 C338 0.1U/10V_4 14.318MHZ
C349 10U/6.3V_6S C344 0.1U/10V_4 C360 0.1U/10V_4 C377 C378 R218
A A
C323 *10U/6.3V_8S C365 0.1U/10V_4 33P/50V_4 33P/50V_4 *10K/F_4
2
2
Place each 0.1uF cap close to pin Place each 0.1uF cap close to pin Place each 0.1uF cap close to pin CPU_SEL
R217
10K/F_4
0 1
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz
(default)
Place within 0.5"
U15
of C/G
5 23 CLK_BUF_BCLK_P_R 4 3
+VDDSE_CLK VDD_LCD CPU-0 CLK_BUF_BCLK_P 8
29 22 CLK_BUF_BCLK_N_R 2 1 CLK_BUF_BCLK_N 8
VDD_REF CPU-0# RP22 0_4P2R_4
+VDDCORE_CLK 1 VDD_USB CPU-1 20
17 VDD_SRC CPU-1# 19
24
+VDDIO_CLK 18
VDD_CPU
VDD_CPU_IO
9LRS3197 DOT96T_LPR 3 CLK_BUF_DREFCLK_R RP23 2 1 0_4P2R_4 CLK_BUF_DREFCLK 8
+3V
B 15 4 CLK_BUF_DREFCLK#_R 4 3 B
VDD_SRC_IO DOT96C_LPR CLK_BUF_DREFCLK# 8
31 13 CLK_BUF_PCIE_3GPLL_R RP20 2 1 0_4P2R_4
8,12,13,26,33 CGDAT_SMB SDATA SRC-1 CLK_BUF_PCIE_3GPLL 8
8,12,13,26,33 CGCLK_SMB 32 14 CLK_BUF_PCIE_3GPLL#_R 4 3 CLK_BUF_PCIE_3GPLL# 8 R220
SCLK SRC-1#
1K/F_4
R198 10K/F_4 16 10 CLK_BUF_DREFSSCLK_R RP19 2 1 0_4P2R_4
+3V CPU_STOP# SATA CLK_BUF_DREFSSCLK 8
8 CLK_ICH_14M CLK_ICH_14M R216 33_4 CPU_SEL 30 11 CLK_BUF_DREFSSCLK#_R 4 3 CLK_BUF_DREFSSCLK# 8
C384 *10P/50V_4 REF_0/CPU_SEL SATA# CK_PWRGD_R
CK_PWRGD_R 25 6 CLK_VGA_27M_NOSS R201 33_4 CLK_27M_NONSS 16
CK_PWRGD/PD#_3.3 27MHz_nonSS CLK_VGA_27M_SS R194 33_4
Place R8044 within 0.5" of C/G 27MHz_SS 7 CLK_27M_SS 16
3
XTAL_OUT 27 Q11
XTAL_IN XOUT 2N7002E
28 33
9
XIN QFN32 GND
26 R219
2
VSS_SATA
VSS_USB
VSS_REF
VSS_CPU
21 FOR SG/DIS 37 VR_PWRGD_CLKEN# 2 100K/F_4
8 VSS_LCD VSS_SRC 12
9LRS3197
1
C C
+1.05V 7,8,9,11,36,37,43
+1.5V 33,41
+3V 3,7,8,9,10,11,12,13,21,22,23,24,25,26,27,28,29,30,31,32,33,34,37,40,41
HOLE CPU H7 H6
*H-TC276BC197D150P2
H9 H4 H19 H18 H16 H3
H-C217D126P2 H-C217D126P2 *H-TC315BC354D118P2
GPU H20 H2 *H-TC236BC354D130P2
*H-TC276BC197D150P2 *H-TC236BC354D130P2
1
1
H14 H10 H13
*H-TC315BC354D118P2 *H-TC315BC354D118P2 *H-TC315BC354D118P2 *H-TC276BC197D150P2 *H-TC276BC197D150P2
1
1
1
1
1
1
H11
H12
1
1
*H-TC276BC197D150P2
1
1
1
D *H-TC276BC197D150P2 D
1
H1 H15 H5 H17 H8 *H-TC276BC197D150P2
1
*H-TC315BC354D118P2 *H-TC315BC354D118P2 *H-TC315BC335D118P2
PAD1 PAD2
*H-TC315BC354D118P2 *H-TC315BC354D118P2 *pad-re236x394np *pad-re236x394np
PROJECT : LX6_LX7
1
1
1
1
1
1
1
SPAD-RE118X197NP SPAD-RE118X197NP Quanta Computer Inc.
Size Document Number Rev
Custom Clock Gen(9LRS3197)/HOLES 1A
NB5
Date: Tuesday, February 02, 2010 Sheet 2 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
DIS SG/UMA
9 DMI_TXN0 A24
U25A
DMI_RX#[0]
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
B26 PEG_COMP R270
A26
B27
49.9/F_4
Ra
Rb
Rc
NA 0 ohm
0 ohm NA
0 ohm NA
03
9 DMI_TXN1 C23 A25 PEG_RBIAS R269 750/F_4
DMI_RX#[1] PEG_RBIAS
9 DMI_TXN2 B22 PEG_RX#[0..15] 14
DMI_RX#[2] PEG_RX#0 U25B
9 DMI_TXN3 A21 K35
DMI_RX#[3] PEG_RX#[0] PEG_RX#1 R400 20/F_4 H_COMP3 AT23
J34 A16 CLK_CPU_BCLK 10
PEG_RX#[1] PEG_RX#2 R401 20/F_4 H_COMP2 AT24 COMP3 BCLK
9 DMI_TXP0 B24 J33 B16 CLK_CPU_BCLK# 10
DMI_RX[0] PEG_RX#[2] PEG_RX#3 R24 49.9/F_4 H_COMP1 G16 COMP2 BCLK#
A 9 DMI_TXP1 D23
B23
DMI_RX[1] PEG_RX#[3]
G35
G32 PEG_RX#4 R405 49.9/F_4 H_COMP0 AT26 COMP1 MISC AR30
A
9 DMI_TXP2 DMI_RX[2] PEG_RX#[4] COMP0 BCLK_ITP
9 DMI_TXP3 A22 F34 PEG_RX#5 AH24 AT30 CLK_PCIE_3GPLL 8
DMI_RX[3] PEG_RX#[5] PEG_RX#6 SKTOCC# BCLK_ITP#
F31 CLK_PCIE_3GPLL# 8
PEG_RX#[6] PEG_RX#7
D24 D35
CLOCKS PEG_CLK E16 Rc
9
9
DMI_RXN0
DMI_RXN1 G24
DMI_TX#[0]
DMI_TX#[1]
DMI PEG_RX#[7]
PEG_RX#[8]
E33 PEG_RX#8
PEG_RX#9
H_CATERR# AK14
CATERR# PEG_CLK#
D16
DREFSSCLK_R
R274 *0_4
9 DMI_RXN2 F23
DMI_TX#[2] PEG_RX#[9]
C33
PEG_RX#10
10 H_PECI AT15
PECI R273 3
Ra 0_4P2R_4
9 DMI_RXN3 H23
DMI_TX#[3] PEG_RX#[10]
D32
B32 PEG_RX#11
32,37 H_PROCHOT# AN26
AK15
PROCHOT# THERMAL DPLL_REF_SSCLK
A18
A17 1
4
2
DREFSSCLK 8
PEG_RX#[11] 10,32 PM_THRMTRIP# THERMTRIP# DPLL_REF_SSCLK# DREFSSCLK# 8
9 DMI_RXP0 D25 C31 PEG_RX#12 Rb
DMI_TX[0] PEG_RX#[12] PEG_RX#13 C801 *0.1U/10V_4 DREFSSCLK#_R R272 *0_4
9 DMI_RXP1 F24 B28
DMI_TX[1] PEG_RX#[13] PEG_RX#14 DDR3_DRAMRST#_C
9 DMI_RXP2 E23 B30 T4 AP26 F6 DDR3_DRAMRST#_C 12
DMI_TX[2] PEG_RX#[14] PEG_RX#15 RESET_OBS# SM_DRAMRST#
9 DMI_RXP3 G23 A31 9 PM_SYNC AL15
DMI_TX[3] PEG_RX#[15] PM_SYNC
PEG_RX0
PEG_RX[0..15] 14 AN14
VCCPWRGOOD_1 DDR3 SM_RCOMP[0] AL1 SM_RCOMP_0 R396 100/F_4
J35 10 H_PWRGOOD AN27 AM1 SM_RCOMP_1 R397 24.9/F_4
PEG_RX[0] VCCPWRGOOD_0
2.7GT/s data rate PEG_RX[1]
H34
H33
PEG_RX1
PEG_RX2
9 PM_DRAM_PWRGD AK13
SM_DRAMPWROK MISC SM_RCOMP[1]
SM_RCOMP[2]
AN1 SM_RCOMP_2 R398
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