Service Manuals, User Guides, Schematic Diagrams or docs for : Compaq-HP DV9000_Schematic
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1 2 3 4 5 6 7 8
PCB STACK UP
LAYER 1 : TOP
RUN POWER
SW
AC/BATT
CONNECTOR PG 34
CPU VR
Altlantis/Apollo
PG 38
LAYER 2 : SGND1 Turion64
A
LAYER 3 : IN1
PG 36,37
BATT
CHARGER PG 34
Sempron
DC/DC
Block Diagram A
LAYER 4 : IN2 +3VSUS
DDRII-SODIMM1 DDRII 667mhz +5VSUS
LAYER 5 : VCC
PG 5 25W/35W
LAYER 6 : IN3 AMD Socket S1 638P PG 33
DDRII-SODIMM2 DDRII 667mhz
LAYER 7 : SGND2 PG 2,3,4
PG 5
LAYER 8 : BOT HT Link
Option for 17" only
PCI-E PCI-Express 16X NVDIA G3-64 for 15.4"
nVIDIA NVDIA G3-128 for 17" HDMI CON
C51M/D PG 18
Integraded VGA Function
Graphics
PG 9,10,11,12,13,14
TV_OUT Mini PCI-E Card Express Card
Cable VGA PCI Express Mini Card (NEW CARD)
TV_OUT
Docking RJ-45 (Wireless LAN/WAN) PG 28
B
CRT/S-VIDEO B
CIR/Pwr btn PG 27 468PIN CRT_OUT
PG 19
SPDIF Out
Stereo MIC LVDS(2 Channel) Panel Connector
SIM CARD PG 6,7,8
www.kythuatvitinh.com
Headphone Jack PG 27 15" / 17" PG 18
USB Port
HT Link
VOL Cntr
PG 31 CLOCK
USB2.0
Option for 17" only
INTERFACE
SATA2 Bluetooth USB2.0 I/O Ports Camera Mini PCI-E Card x1
SATA - HDD nVIDIA PG 28 PG 26 1.3MP PG 23 Express Card x1
X3
PG 28 MCP51M Cable Docking x1
Digitally signed by 508PIN PCI BUS / 33MHz
SATA0
fdsf SATA - HDD
LAN
PG 26
C
DN: cn=fdsf, Azalia
C
PATA (66/100/133) PG 15,16,17
o=fsdfsd, ou=ffsdf, CD-ROM
PATA-
Two-element
REALTEK RICOH
PG 26 RTL8201CL RICOH 832
email=fdfsd@fsdff, Conexant
microphone (10/100)/
PG 23 REL8211B
c=US LPC
Venice AMOM
(10/100 /Gigabit) PG 21
CX20549-12 Audio Jacks
Date: 2009.10.17 PG 23 (Phone/SPDIF/
PG 20
11:12:44 +07'00' Keyboard MIC)
PG 23
Touch Pad PG 29 ENE KBC IEEE1394 Memory
RJ45 CardReader
VAULE DEFINE CONN
KB3920 Bx
A=0603,B=0805,C=1206,F=1%, CIR AUDIO MDC DAA
OTHER IS 0402 PG 23 PG 21 PG 22
Amplifier PG 20
PG 25 PG 24
Capacitive Sense
EXAMPLE PG 30
SW PG 29 PCI ROUTING
IDSEL INTERUPT DEVICE
10R=10ohm(0402) TABLE
Jack to
X-Bus
D
10A=10ohm(0603) MODEM RJ 11 REQ0# / GNT0# AD21 INTA#,INTB# RICOH832 D
Speaker
10B=10ohm(0805)
PG 25 PG 20
10C=10ohm(1206)
10/F=10ohm(0402 and 1%) FAN Flash PROJECT : AT8
Quanta Computer Inc.
PG 31 PG 30 Size Document Number Rev
Custom Block Diagram 1A
NB5/RD2/HW1
Date: Wednesday, June 14, 2006 Sheet 1 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
HT_RXD#[15..0] HT_TXD[15..0]
02
6 HT_RXD#[15..0] 6 HT_TXD[15..0] W/S= 15 mil/20mil
HT_RXD[15..0] HT_TXD#[15..0] CPU2.5V L80 FBMJ3216HS800-T
6 HT_RXD[15..0] 6 HT_TXD#[15..0] 2.5V
U26A C43 .22U 1 2
C703 .22U 1.2V_HT D1 AE2 1.2V_HT C707 4.7UA
C706 4.7UA 1.2V_HT V_HT0_A1 V_HT0_B1 1.2V_HT C705 180P/50V C711 100U/6032
D2 V_HT0_A2 V_HT0_B2 AE3 U26E
C702 4.7UA 1.2V_HT D3 AE4 1.2V_HT C709 180P/50V
C704 .22U 1.2V_HT V_HT0_A3 V_HT0_B3 1.2V_HT CPUTEST2 CPU2.5V C712 4.7UA
D4 V_HT0_A4 V_HT0_B4 AE5 1.2V_HT T14 AB6 TEST2 VDDA_1 F9
CPUTEST3 Y6 F8 CPU2.5V C52 3300P/X7R
T158 TEST3 VDDA_2
HT_RXD0 E3 AD1 HT_TXD0 CPU_THERMDA W8
HT_RXD1 HT_RXD0 HT_TXD0 HT_TXD1 CPU_THERMDC THERMDA HTCPU_RST1# R457 *300R
E1 HT_RXD1 HT_TXD1 AC2 W7 THERMDC RESET# B7 1.8VSUS
HT_RXD2 G3 AB1 HT_TXD2 CPUTEST6 AA6 A7 HTCPU_PWROK1 R460 *300R
HT_RXD2 HT_TXD2 T2 TEST6 PWROK 1.8VSUS
HT_RXD3 G1 AA2 HT_TXD3 CPUTEST7 C3 F10 HTCPU_STOP1# R450 *300R
A HT_RXD3 HT_TXD3 T164 TEST7 LDTSTOP# 1.8VSUS A
HT_RXD4 J1 W2 HT_TXD4 CPUTEST8 C4
HT_RXD4 HT_TXD4 T1 TEST8
HT_RXD5 L3 V1 HT_TXD5 C2
HT_RXD6 HT_RXD5 HT_TXD5 HT_TXD6 CPUTEST10 TEST9 CPUHTREF0 R437 44.2F
L1 HT_RXD6 HT_TXD6 U2 T159 K8 TEST10 HTREF0 R6
HT_RXD7 N3 T1 HT_TXD7 T12 CPUTEST12 AC8 P6 CPUHTREF1 R436 44.2F
HT_RXD7 HT_TXD7 TEST12 HTREF1 1.2V_HT
HT_RXD8 E5 AD4 HT_TXD8 AA7 F6 CPU_CORE_FB
HT_RXD8 HT_TXD8 TEST13 VDD_FB CPU_CORE_FB 38
HT_RXD9 F3 AD5 HT_TXD9 T9 CPUTEST14 C7 E6 CPU_CORE_FB#
HT_RXD9 HT_TXD9 TEST14 VDD_FB# CPU_CORE_FB# 38
HT_RXD10 G5 AB4 HT_TXD10 T5 CPUTEST15 F7 W9 CPU_SUS_FB
HT_RXD10 HT_TXD10 TEST15 VDDIO_FB CPU_SUS_FB 37
HT_RXD11 H3 AB5 HT_TXD11 CPUTEST16 E7 Y9
HT_RXD11 HT_TXD11 T3 TEST16 VDDIO_FB#
HT_RXD12 K3 Y5 HT_TXD12 TEST PU/PL MUST CPUTEST17 D7 A9 CPUCLKIN
HT_RXD12 HT_TXD12 T7 TEST17 CLKIN T173
HT_RXD13 L5 V4 HT_TXD13 FOLLOW ERRATUM R58 300R CPUTEST18 H10 A8 CPUCLKIN#
HT_RXD13 HT_TXD13 TEST18 CLKIN# T170
HT_RXD14 M3 V5 HT_TXD14 R53 300R CPUTEST19 G9 G10 CPU_DBRDY
HT_RXD14 HT_TXD14 133 TEST19 DBRDY T39
HT_RXD15 N5 T4 HT_TXD15 T162 CPUTEST20 AF7 E10 CPU_DBRDY#
HT_RXD15 HT_TXD15 TEST20 DBREQ# T31
REVISION GUIDE R48 300R CPUTEST21 AB8 AA9 CPU_TMS
TEST21 TMS T18
HT_RXD#0 E2 AC1 HT_TXD#0 FROM AMD NPT T165 CPUTEST22 AE8 AC9 CPU_TCK
HT_RXD#0 HT_TXD#0 TEST22 TCK T167
HT_RXD#1 F1 AC3 HT_TXD#1 T160 CPUTEST23 AD7 AD9 CPU_TRST#
HT_RXD#1 HT_TXD#1 0Fh CPU TEST23 TRST# T174
HT_RXD#2 G2 AA1 HT_TXD#2 T161 CPUTEST24 AE7 AF9 CPU_TDI
HT_RXD#2 HT_TXD#2 TEST24 TDI T176
HT_RXD#3 H1 AA3 HT_TXD#3 R55 510F CPUTEST25 E9 AE9 CPU_TDO
HT_RXD#3 HT_TXD#3 1.8VSUS TEST25 TDO T175
HT_RXD#4 K1 W3 HT_TXD#4 R49 510F CPUTEST25# E8 AC6 CPU_PRES# R425 1K
HT_RXD#4 HT_TXD#4 TEST25# CPU_PRESENT# 1.8VSUS
HT_RXD#5 L2 U1 HT_TXD#5 R429 300R CPUTEST26 AE6 A3
HT_RXD#5 HT_TXD#5 1.8VSUS TEST26 PSI# CPU_PSI# 38
HT_RXD#6 M1 U3 HT_TXD#6 T169 CPUTEST27 AF8 B5 CPU_VID0_L
HT_RXD#6 HT_TXD#6 TEST27 VID0 1.8VSUS
HT_RXD#7 N2 R1 HT_TXD#7 CPUTEST28 J7 C5 CPU_VID1_L R33 *300R
HT_RXD#7 HT_TXD#7 T4 TEST28 VID1
HT_RXD#8 F5 AD3 HT_TXD#8 CPUTEST28# H8 A4 CPU_VID2_L R30 300R
HT_RXD#8 HT_TXD#8 T6 TEST28# VID2
HT_RXD#9 F4 AC5 HT_TXD#9 FBCLKOUT C9 A6 CPU_VID3_L R21 *300R
HT_RXD#10 HT_RXD#9 HT_TXD#9 HT_TXD#10 R52 80.6F FBCLKOUT# TEST29 VID3 CPU_VID4_L R37 *300R
H5 HT_RXD#10 HT_TXD#10 AB3 C8 TEST29# VID4 C6
HT_RXD#11 H4 AA5 HT_TXD#11 A5 CPU_VID5_L R31 *300R
HT_RXD#12 HT_RXD#11 HT_TXD#11 HT_TXD#12 VID5 CPU_SID R23 *300R
K4 HT_RXD#12 HT_TXD#12 W5 ROUTE TRACES 80OHM DIFF SID AF5
HT_RXD#13 M5 V3 HT_TXD#13 IMPEDENCE 8/5/20 SPACING AF4 CPU_SIC
HT_RXD#14 HT_RXD#13 HT_TXD#13 HT_TXD#14 SIC CPU_PROCHOT#
M4 HT_RXD#14 HT_TXD#14 U5 PROCHOT# AC7 1.8VSUS
HT_RXD#15 P5 T3 HT_TXD#15 AF6 CPU_THERMIP# R426 300R
HT_RXD#15 HT_TXD#15 THERMTRIP# 1.8VSUS
B B3 R433 300R B
HT_CPU_UPCLK0 HT_CPU_DWNCLK0 RSVD_1
6 HT_CPU_UPCLK0 J3 HT_RXCLK0 HT_TXCLK0 Y1 HT_CPU_DWNCLK0 6 H19 RSVD_2 RSVD_12 R22
HT_CPU_UPCLK1 J5 Y4 HT_CPU_DWNCLK1 1.8VSUS H18 H16
6 HT_CPU_UPCLK1 HT_RXCLK1 HT_TXCLK1 HT_CPU_DWNCLK1 6 RSVD_3 RSVD_13
W18 R23 CPUCLKIN C716 3900P
RSVD_4 RSVD_14 CPU_CLK 6
HT_CPU_UPCLK#0 J2 W1 HT_CPU_DWNCLK#0 CPU_SID R428 *300R D5 R25
6 HT_CPU_UPCLK#0 HT_RXCLK#0 HT_TXCLK#0 HT_CPU_DWNCLK#0 6 CPU_SIC RSVD_5 RSVD_15
HT_CPU_UPCLK#1 K5 Y3 HT_CPU_DWNCLK#1 R427 *300R N20 B18 CPUCLKIN# C714 3900P
6 HT_CPU_UPCLK#1 HT_RXCLK#1 HT_TXCLK#1 HT_CPU_DWNCLK#1 6 RSVD_6 RSVD_16 CPU_CLK# 6
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R422 300R P20 R24
HT_CPU_UPCTL0 HT_CPU_DWNCTL0 RSVD_7 RSVD_17 CPUCLKIN# R446 169F CPUCLKIN
6 HT_CPU_UPCTL0 N1 HT_RXCTL0 HT_TXCTL0 R2 HT_CPU_DWNCTL0 6 P19 RSVD_8 RSVD_18 C1
1.2V_HT HT_CPU_UPCTL1 P3 T5 HT_CPU_DWNCTL1 N19 H6
R435 49.9F HT_RXCTL1 HT_TXCTL1 T157 RSVD_9 RSVD_19
P22 RSVD_10 RSVD_20 G6 KEEP TRACE RESISTOR <0.6" FROM CPU
6 HT_CPU_UPCTL#0 P1 HT_RXCTL#0 HT_TXCTL#0 R3 HT_CPU_DWNCTL#0 6 If AMD SI is not used R26 RSVD_11 RSVD_21 AA8 AND TRACE TO AC CAP <1.25"
HT_CPU_UPCTL#1 P4 R5 HT_CPU_DWNCTL#1 SID can be left, SIC
R434 49.9F HT_RXCTL#1 HT_TXCTL#1 T156
300ohm to VSS. AMD S1 SOCKET CPUVID1 PU REQUIRED
AMD S1 SOCKET FOR COMPATIBILITY WITH
FUTURE CPU
HT_RXCTL1/HT_RXCRL#1 MUST <1.5" FROM CPU PIN
MUST KEEP LOW DURING S3-S5 TO MEET HT IO LINK SPEC
CPU THERMAL SENSOR & CONTROL HT LINK CONTROL LEVEL SHIFTER OVER TEMP CONTROL
Q35
3V R62 200R 6648VCC C88 .1U PDTC144EU
1.8VSUS
CPU_THERMIP# 1 3 MCP_THERMIP# 17
5
U1 U25
10/20mils 6 HTCPU_RST# 2
3V R64 2.7K LM86_SMC 8 1 4 HTCPU_RST1# PLACE CLOSE CPU
SCLK VCC CPU_THERMDA THERM_ALERT#
11,17,30 ECPWROK 1
R63 2.7K LM86_SMD 7 2 D31 CH500H
2
SDA DXP C120 74LVC1G08GW 3V
3
C THERM_ALERT# C
6 3 2200P/X7R R423 4.7K
ALERT# DXN 1.8VSUS
1.8VSUS
4 5 CPU_THERMDC
17 THERM_OVER# OVERT# GND
5
U28 CPU OT THERM IC THERMTRIP TO SHUTDOWN SYS FROM SB
R72 *10K 2
3V 6 HTCPU_PWRGD
MAX6657 4 HTCPU_PWROK1
R73 10K G781P8 ECPWROK 1
3V
ADDRESS: 98H THERM_OVER# 1 3 CPU_PROCHOT#
74LVC1G08GW
3
Q36
29,30,34 MBCLK 3 1 LM86_SMC 30 EC_PROCHOT# PDTC144EU
LM86_SMC 5 1.8VSUS
Q8 D29
5
RHU002N06 U24 CH500H
2
6 HTCPU_STOP# 2 5 DIMM_THEM#
2
5 LM86_SMD LM86_SMD 1 3 4 HTCPU_STOP1# D30
MBDATA 29,30,34
ECPWROK 1 *CH500H 3V
3V Q9
RHU002N06 74LVC1G08GW CPU PROCHOT INPUT FROM THERMAL IC OR SODIMM SENSOR
2
3
MBCLK/MBDATA NEED PU TO 3VPCU FOLLOW AMD AND NVIDIA RECOMMEND
3V
NEED TO CONFIRM NVIDIA FOR THE USAGE CONNECTION TO SB
CPU_VID3_L R43 0A
CPU_VID3 17,38
D D
CPU_VID2_L R18 0A
CPU_VID2 17,38
CPU_VID4_L R40 0R
CPU_VID4 17,38
CPU_VID5_L R39 0A
CPU_VID1_L R19 0A
CPU_VID5 17,38
PROJECT : AT8
CPU_VID0_L R38 0R
CPU_VID1 17,38
Quanta Computer Inc.
CPU_VID0 17,38
Size Document Number Rev
Custom CPU(HT_LINK /CTL) 2A
NB5/RD2/HW1
Date: Wednesday, June 14, 2006 Sheet 2 of 39
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