Service Manuals, User Guides, Schematic Diagrams or docs for : Compaq-HP HP DV1000,DV1700
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1 2 3 4 5 6 7 8
PCB STACK UP
LAYER 1 : TOP
CT6 BLOCK DIAGRAM
LAYER 2 : GND
CPU THERMAL Calistoga / Yonah /ICH-7m
LAYER 3 : IN1 SENSOR
A
LAYER 4 : IN2 CPU Yonah/Merom PG 5 14.318MHz A
SYSTEM POWER MAX1845
LAYER 5 : VCC CPUCLK, (1.2V/NB_CORE/1.25V)
XXX Pins (uPGA) CPUCLK# PG 38
LAYER 6 : BOT CLOCK GEN
PG 3,4 IDTXXX/ ICSXXXX
SBLINKCLK, SBLINKCLK# CPU CORE MAX1544
56pins POWER VCORE 1.2V /44A
HyperThansport I/O BUS NBSRCCLK, NBSRCCLK# PG 39
Link 16x16 HTREFCLK
CABLE DOCK
PG 2 SYSTEM MAX1999
PG 30 POWER(3/5V)
R.G,B OSC14M PG 36
Daughter Board CRT port
PG 29
TV, USB, BLUE TOOTH NORTH BRIDGE SYSTEM POWER MAX1845
LVDS X1 DDRII DDRII-SODIMM1
PG 31
LCD Panel Calistoga 266,333 MHz (1.8VSUS/0.9V SMDDR_VREF)
PG 18 XXX BGA
Power Board INTEGRADED VGA FUNCTION DDRII PG 12,13 PG 37
B
PG 31 TV-OUT 266,333 MHz B
S-VIDEO PG 6,7,8,9,10,11 DDRII-SODIMM2 BATT CHARGER
PG 18 MAX1722
PG 12,13 PG 35
DMI LINK
32.768KHz 2X
PCI-E DISCHARGE
NBSRCCLK, NBSRCCLK# PG 34
USB PORT 0, 1, 2 USB 2.0
33MHZ, 3.3V PCI
PG 21
PCLK_E
1st SATA - HDD SATA 150MB ICH-7m 24.576MHz
PG 32
XXX BGA Azalia
2nd IDE - CDROM
ATA 66/100/133 LAN
PWRCLKP Azalia MINI-Card CARDREADER / IEEE 1394
PG 31 PWRCLKN Intel CONTROLLER/CF
PG 14,15,16,17 DIB_DATAN CX20551-22
C
DIB_DATAP MBAMC20493-010 Ekron C
82562GT RICOH 832
PG 22 PG 25 PG 33 PG 19,20,21
LPC PCLK_E
PCI DEVICES IRQ ROUTING 32.768KHz
25MHz
3.3V LPC, 33MHz
DEVICE IDSEL # REQ/GNT # PCI_INT
INTEL ETHERNET AD24 (D8) C(A~E)
MINIPCI SLOT AD22 1 C,D Express Card x1 SMARTDAA AMP 5 IN 1 1394
CardBus/1394 AD25 0 E,F,G NEW CARD MODEM, CARD CONN
PC87541L TPA0312 READER
SD/MMC,
TQFP XXX PG 33 PG 24 PG 23 SM, MS, XD
PG 28 PG 21 PG 20
WIRE
RJ11 JACK RJ45
D FAN Touchpad Keyboard FLASH HEADPHONE, D
JACK JACK
2ND HEADPHONE,
PG 29 PG 31 PG 31 PG 27 MIC
PG 24 PG 23 PG 25
PROJECT : CT6
Quanta Computer Inc.
Size Document Number Rev
CustomBLOCK DIAGRAM 1B
Date: Friday, September 23, 2005 Sheet 1 of 44
1 2 3 4 5 6 7 8
A B C D E
FSC FSB FSA CPU SRC PCI L35
ACB2012L-120-T
1 0 1 100 100 33 +3V VDD_SRC_CPU 25 mils
0 0 1 133 100 33 Default 120 ohms@100Mhz C380 C378 C372 C370 C382
0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 10U
0 1 1 166 100 33
0 1 0 200 100 33 +3V R318 2.2/FVDD_A
5,9,13,14,15,16,17,18,22,23,26,28,29,30,31,32,33,34,36,39,41,42 +3V
0 0 0 266 100 33 +1.05V C373 C374 Use 33R/1%
14,17,38,42 +1.05V
0.1U/10V 10U
1 0 0 333 100 33 VDD_A
4 Close to IC <500mils 4
1 1 0 400 100 33 C358 33P/0402 CG_XIN
1 1 1 200 100 33 Place these termination to close CK410M.
2
37
38
Y4 CL=20 - 22P U15
25 mils 14.318MHZ 50 52 14M_REF R301 33
VDDA
GNDA
XTAL_IN REF0 14M_ICH 16
L32 SMbus address D2 /IDT RP38
ACB2012L-120-T C357 33P/0402 CG_XOUT RHCLK_CPU 2 33X2
1
49 XTAL_OUT CPU0 44 1 CLK_CPU_BCLK 3
VDD_PCI +3V R534 *10K 43 RHCLK_CPU# 3 4 C359
+3V CPU0# CLK_CPU_BCLK# 3
RP41 *10P
120 ohms@100Mhz C360 C362 C356 39 VR_PWRGD_CK410# VR_PWRGD_CK410# 10 41 RHCLK_MCH 1 2 33X2
Vtt_PwrGd#/PD CPU1 CLK_MCH_BCLK 6
0.1U/10V 0.1U/10V 10U 16 PM_STPPCI# PM_STPPCI# 55 40 RHCLK_MCH# 3 4
PCI/SRC_STOP# CPU1# CLK_MCH_BCLK# 6
16 PM_STPCPU# PM_STPCPU# 54 CPU_STOP#
CPU2_ITP/SRC7 36 T66 Place these termination
R300 2.2/FVDD_48 CGCLK_SMB 35
12,13,33 CGCLK_SMB CPU2#_ITP/SRC7# T67
C368 C366 12,13,33 CGDAT_SMB
CGDAT_SMB
CLK_PCIE_MINI_
RP44 to close CK410M.
46 SCLK CK-410M SRC6 33 1 2 33X2 CLK_PCIE_MINI 33
0.1U/10V 10U 16 CLKUSB_48 R127 33 47 32 CLK_PCIE_MINI_# 3 4 CLK_CPU_BCLK R304 49.9/F/B
SDATA SRC6# CLK_PCIE_MINI# 33
RP46 CLK_CPU_BCLK# R307 49.9/F/B
CLK_BSEL0 R122 2.2K/B 12 31 RSRC_MCH 1 2 33X2
FSA/USB_48MHz SRC5 CLK_PCIE_3GPLL 8
CLK_BSEL1 16 30 RSRC_MCH# 3 4 CLK_MCH_BCLK R310 49.9/F/B
FSB/TEST_MODE SRC5# CLK_PCIE_3GPLL# 8
R299 1 VDD_REF CLK_BSEL2 R110 4.7K 53 RP45 CLK_MCH_BCLK# R313 49.9/F/B
FSC/REF1 RSRC_SATA
SRC4_SATA 26 3 4 33X2 CLK_PCIE_SATA 14
C364 C363 VDD_REF 48 27 RSRC_SATA# 1 2
VDD_REF SRC4#_SATA CLK_PCIE_SATA# 14
0.1U/10V 10U VDD_SRC_CPU 42 RP43
VDD_CPU CLK_PCIE_NEW
SRC3 24 3 4 33X2 CLK_PCIE_NEW_C 33
VDD_PCI 1 25 CLK_PCIE_NEW# 1 2
VDD_PCI_1 SRC3# CLK_PCIE_NEW_C# 33
7 RP42
VDD_PCI_2 RSRC_ICH
3
SRC2 22 3 4 33X2 CLK_PCIE_ICH 15
3
VDD_SRC_CPU 21 23 RSRC_ICH# 1 2 CLK_PCIE_3GPLL R328 49.9/F/B
VDD_SRC0 SRC2# CLK_PCIE_ICH# 15
+3V 28 CLK_PCIE_3GPLL# R330 49.9/F/B
VDD_SRC1
Use 1% R 34 VDD_SRC2 SRC1 19 T65
20 CLK_PCIE_SATA R327 49.9/F/B
SRC1# T68
VDD_48 11 RP40 CLK_PCIE_SATA# R329 49.9/F/B
VDD_48 R_DREFSSCLK
SRC0/DREFSSCLK 17 3 4 33X2 DREFSSCLK 8
Iref=5mA, R314 475/F IREF 39 18 R_DREFSSCLK# 1 2
IREF SRC0#/DREFSSCLK# DREFSSCLK# 8
Q30 R303 R308 Ioh=4*Iref CLK_PCIE_MINI R324 49.9/F/B
2
RHU002N06 10K 10K 5 R_PCLK_591 R118 33 CLK_PCIE_MINI# R326 49.9/F/B
PCI5 PCLK_591 28
4 R_PCLK_7411 R114 33
PCI4 PCI_CLK_7411 19
3 1 CGDAT_SMB RP39 3 R_PCLK_LAN R109 33
GND_PCI_1
GND_PCI_2
16,33 PDAT_SMB PCI3 PCLK_LAN
GND_SRC
GND_CPU
DREFCLK R_DOT96 PCLK_MINI_LPC R526 *22 CLK_PCIE_ICH R316 49.9/F/B
GND_REF
8 DREFCLK 1 2 14 DOT96MHz PCI2 56 PCLK_MINI 41
GND_48
DREFCLK# 3 4 R_DOT96# 15 9 R_PCLK_ICH R123 33 R527 22 CLK_PCIE_ICH# R317 49.9/F/B
8 DREFCLK# DOT96MHz# PCIF1/100_96M# PCLK_LPC_DEBUG 28,33
8 R_PCLK_SIO
PCIF0/ITP_EN PCLK_ICH 15
33X2
+3V
ICS954206AG-T
13
51
29
45
Q31 R120 10K
2
6
+3V
2
RHU002N06 CLK_PCIE_NEW_C R321 49.9/F/B
Use 1% R CLK_PCIE_NEW_C# R325 49.9/F/B
3 1 CGCLK_SMB R124 *10K
16,33 PCLK_SMB +3V
R125 10K
DREFSSCLK R312 49.9/F/B
DREFSSCLK Frequency Select. DREFSSCLK# R315 49.9/F/B
"0" : 96MHz
BSEL strappings need to be set for 533MHz Moby Dick (Intel?915GM - Calistoga Interposer) "1" : 100MHz DREFCLK R306 49.9/F/B
2 DREFCLK# R309 49.9/F/B 2
(if Calistoga is designed for 667MHz board).
+1.05V R111 56/F IDT CV140 /56pins
ICS954206AGT /56pins
R112 0 CLK_BSEL0 R117 1K MCH_BSEL0 8
3 CPU_BSEL0
R116 1K
R113 *0
PCLK_591
PCLK_591 28
XDP_OBS2 R106 0 PCI_CLK_7411
XDP_BPM#1 3 PCI_CLK_7411 19
PCLK_LAN
+3V PCLK_LAN
PCLK_ICH
PCLK_ICH 15
+1.05V R104 1K
C159 C154 C152 C158
R101 0 CLK_BSEL1 R103 1K MCH_BSEL1 8 *0.1U/10V*0.1U/10V*0.1U/10V*0.1U/10V
3 CPU_BSEL1
R105 *0
R108 *0
C540 C542
XDP_OBS1 R100 0 XDP_BPM#2 3 0.1U/10V 10U
Stuff 0 ohm for 533MHz, NC for 667MHz
1 1
+1.05V R107 1K 3VPCU
Cross moat
R99 0 CLK_BSEL2 R98 1K
3 CPU_BSEL2 MCH_BSEL2 8
R102 *0
R97 *0
PROJECT : CT6
XDP_OBS0 R96 0 Check Intel
Quanta Computer Inc.
XDP_BPM#3 3
Size Document Number Rev
Custom CLOCK GENERATOR 1A
Date: Friday, September 23, 2005 Sheet 2 of 44
A B C D E
5 4 3 2 1
T4 PAD
U7A
6 H_A#[31:3] +1.05V
H_A#3 J4 H1
A[3]# ADS# H_ADS# 6
H_A#4 L4 E2
A[4]# BNR# H_BNR# 6
H_A#5 M3 G5 +1.05V +1.05V 14,17,38,42
A[5]# BPRI# H_BPRI# 6
H_A#6 K5
H_A#7 M1 A[6]#
A[7]# DEFER# H5 H_DEFER# 6
ADDR GROUP 0
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 6
H_A#9 J1 E1 R38 Near to MCH <500mils
A[9]# DBSY# H_DBSY# 6
H_A#10 N3 56/F
CONTROL
H_A#11 P5 A[10]#
A[11]# BR0# F1 H_BREQ#0 6
D H_A#12 P2 D
H_A#13 L1 A[12]#
A[13]# IERR# D20 6 H_D#[63:0] H_D#[63:0] 6
H_A#14 P4 B3
A[14]# INIT# H_INIT# 14
H_A#15 P1 T133 PAD U7B
H_A#16 R1 A[15]# H_D#0 E22
A[16]# LOCK# H4 H_LOCK# 6 D[0]# D[32]# AA23 H_D#32
L2 H_D#1 F24 AB24 H_D#33
6 H_ADSTB#0 ADSTB[0]# H_CPURST# 6 D[1]# D[33]#
B1 H_D#2 E26 V24 H_D#34
6 H_REQ#[4:0] RESET# D[2]# D[34]#
H_REQ#0 K3 F3 H_RS#0 H_D#3 H22 V26 H_D#35
REQ[0]# RS[0]# D[3]# D[35]#
DATA GRP 0
H_REQ#1 H_RS#1 H_D#4 F23 W25 H_D#36
DATA GRP 2
H2 REQ[1]# RS[1]# F4 D[4]# D[36]#
H_REQ#2 K2 G3 H_RS#2 H_RS#[2:0] 6 H_D#5 G25 U23 H_D#37
H_REQ#3 REQ[2]# RS[2]# H_D#6 E25 D[5]# D[37]#
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