Service Manuals, User Guides, Schematic Diagrams or docs for : Compaq-HP HP G60 COMPAQ CQ60 - WISTRON HBU16 1.2 - REV 1

<< Back | Home

Most service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.

Image preview - the first page of the document

>> Download HP G60 COMPAQ CQ60 - WISTRON HBU16 1.2 - REV 1 documenatation <<

Text preview - extract from the document
               5                                    4                                                                          3                                                    2                                                               1

                                                                                                                                                                                                                                               SYSTEM DC/DC
                              HBU16-1.2 Intel UMA Block Diagram                                                                                                                                                                             INPUTS

                                                                                                                                              Project code : 91.4FQ01.001                                                                   DCBATOUT

                                                                                                   Intel CPU                                                                                                                                                               +3VALW

                            Clock Generator
                                                                                                                                              PCB P/N : 09233                                                                                                              +3VL
D                                                                                                                                                                                                                                                                                           37   D
                                                                                           Penryn SV                                          Revision : 1        SYSTEM DC/DC
                                                                                                                                                                                                                                               SYSTEM DC/DC
                                                                                                                            3,4,5                                                                       APL5912
                                                                                                                                                                                                                                            INPUTS                    OUTPUTS
                                                                                                                                                                                               INPUTS                 OUTPUTS
                                                                                                              FSB                                                                                                                                                     +0.9VS
                                                                                                                                                                                               +1.8V                  +1.5VS                DCBATOUT
                                                                                                              800/1066MHz                                                                                                            40                               +1.8V
                                                                                                                                              RGB CRT
                             DDRII                                                                                                                                         1600X1200@75
                                                                                                                                                                                                                                               SYSTEM DC/DC
                                     Slot 0    DDRII 667/800 Channel A             Cantiga-GM/GL                                                                                                                                                         RT8209
                             667/800      12
                                                                                   AGTL+ CPU I/F                   DDR I/F                    LVDS(Dual Channel)
                                                                                                                                                                                                                                            INPUTS                    OUTPUTS
                                                                                   INTEGRATED GRAHPICS
                                                                                                                                                                             WXGA+      15
                            DDRII              DDR II 667/800 Channel B                                                                                                                                                                     +5VALW                    +1.05V
                                      Slot 1                                                                                                                                                                                                                                                39
                            667/800       13
                                                                                   LVDS, CRT I/F
                                                                                                                                              PCIE                            HDMI
                                                                                                                                                                                        26                                                  MAXIM CHARGER
C                                                                                                                                                                                                                                                                                                C
                                                                          DMIx4                                              C-LINK                                                                                                         INPUTS                  OUTPUTS
                                                                                                                                                                                             WEBCAM                                         DCBATOUT               18V 3.0A
                                                                                                                                                                                                               15                                                  5V 100mA

      SD/MMC                   Realtek                   USB 2.0
                                                                                                    INTEL                                                                                    BLUETOOTH
      MS/MS Pro/xD             RTS5159                                                                                                                                                                         22                                   CPU DC/DC
                   25                     25
                                                                                                   ICH9-M                                     USB 2.0                                        USB x 3
                               Realtek                                                                                                                                                                                                       INPUTS                 OUTPUTS
      RJ45                                                                                 12 USB 2.0/1.1 ports
                               RTL8103T                  PCIE
      CONN                                                                        ETHERNET (10/100/1000Mb)                                                                                                                                                          +VCC_CORE
                   27          10/100     23                                                                                                  SATA                                           HDD                                             DCBATOUT
                                                                                           High Definition Audio                                                                                               22                                                  0.844~1.3V
                                                                                                   4 SATA ports                                                                                                                                                    22A
                                AMOM                                                               6 PCIE ports
                                                                                                      ACPI 1.1
      RJ11                     MODEM                                                                                                                                                                           22
      CONN                    CX20548-11Z           HD AUDIO                                          LPC I/F
                                                                                                                                              LPC Bus
                                                                                                                                                                                                                                               PCB LAYER                                         B

                                                                                                   PCI/PCI BRIDGE
                                                                                                                                                                                                                                            L1:          Signal 1
                               HD AUDIO                                                                       17,18,19,20,21
                               CODEC                                                                                                                                                                                                        L2:          GND
        LINE OUT
                                          28                                                                                                                  KBC                                                                           L3:          Signal 2
                                                                                    PCIE+USB 2.0

                                                                                                                                        SPI                WINBOND

                                                                                                                                                                                                                                            L4:          Signal 3
             MIC IN                                                                                                                                           WPCE773L         29
                                                                                                                                                                                                                                            L5:          VCC
                                                                                                                                                                                                                                            L6:          Signal 4
                                                                             Mini-Card                      Flash ROM               Flash ROM        Touch         Int.
                                                                                                                                                                                        & Fan
                                                                            802.11a/b/g/n                      64KB                    2MB           PAD           KB
                                                                                                    26                         19             31         30           30
                                                                                                                                                                                        GMT G7921
A                                                                                                                                                                                                                                                                                                A
              2CH SPEAKER
                                                                                                                                                                                                                                          Wistron Corporation
                                                                                                                                                                                                                                          21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
                                                                                                                                                                                                                                          Taipei Hsien 221, Taiwan, R.O.C.


                                                                                                                                                                                                                                Block Diagram
                                                                                                                                                                                                     Size      Document Number                                                     Rev
                                                                                                                                                                                                                                      HBU16 1.2                                         1
                                                                                                                                                                                                     Date:   Monday, July 06, 2009               Sheet      1         of           41
               5                                    4                                                                          3                                                    2                                                               1
                            A                                          B                                                    C                                              D                                                                       E
ICH9M Functional Strap Definitions                                                              ICH9 Integrated pull-up                                      Cantiga chipset and ICH9M I/O controller
                                                                                      page 92
                                                   ICH9 EDS 642879      Rev.1.5
                                                                                                and pull-down Resistors                                      Hub strapping configuration
    Signal      Usage/When Sampled                      Comment
                                                                                                                           ICH9 EDS 642879     Rev.1.5                    Montevina Platform Design guide 22339 0.5                                                       page 218
    HDA_SDOUT   XOR Chain Entrance/     Allows entrance to XOR Chain testing when TP3
                PCIE Port Config1 bit1, pulled low. When TP3 not pulled low at rising edge              SIGNAL               Resistor Type/Value             Pin Name   Strap Description                                      Configuration
                Rising Edge of PWROK.   of PWROK, sets bit1 of RPC.PC (Cofig Registers:                                                                      CFG[2:0]   FSB Frequency Select 000 = FSB1067
                                                                                                CL_CLK[1:0]                  PULL-UP 20K
                                        offset 224h). This signal has weak internal                                                                                                          011 = FSB667
                                        pull-down.                                              CL_DATA[1:0]                 PULL-UP 20K                                                     010 = FSB800
                                                                                                                                                                                             others = Reserved
4   HDA_SYNC    PCIE config1 bit0,      This signal has a weak internal pull-down.
                                                                                                CL_RST0#                     PULL-UP 20K
                                                                                                                                                             CFG[4:3]   Reserved
                Rising Edge of PWROK.   Sets bit0 of PRC.PC (Config Registers: Offset           DPRSLPVR/GPIO16              PULL-DOWN 20K                   CFG8
                                        224h).                                                                                                               CFG[15:14]
                                                                                                ENERGY_DETECT                PULL-UP 20K                     CFG[18:17]
    GNT2#/      PCIE config2 bit2,      This signal has a weak internal pull-up.                HDA_BIT_CLK                  PULL-DOWN 20K                   CFG5       DMI x2 Select                0 = DMI x2
    GPIO53      Rising Edge of PWROK.   Sets bit2 of PRC.PC2 (Config Registers: Offset                                                                                                               1 = DMI x4 (Default)
                                        224h).                                                  HDA_DOCK_EN#/GPIO33          PULL-UP 20K
                                                                                                                                                             CFG6       iTPM Host Interface          0 = The iTPM Host Interface is enabled (Note 2)
                                                                                                HDA_RST#                     PULL-DOWN 20K                                                           1 = The iTPM Host Interface is disabled (default)
    GPIO20      Reserved.               This signal should not be pulled high.
                                                                                                HDA_SDIN[3:0]                PULL-DOWN 20K                   CFG7       Intel Management             0 = Transport Layer Security (TLS) cipher
    GNT1#/      ESI Strap (Server Only) ESI compatible mode is for server platforms only.                                                                               engine crypto strap              suite with no confidentiality
    GPIO51      Rising Edge of PWROK.   This signal should not be pulled low for desktop        HDA_SDOUT                    PULL-DOWN 20K                                                           1 = TLS cipher suite with confidentiality(Default)
                                        and mobile.                                                                                                          CFG9       PCIE Graphics Lane           0 = Reserved Lanes, 15->0, 14->1 ect..
                                                                                                HDA_SYNC                     PULL-DOWN 20K
                                                                                                                                                                                                     1 = Normal operation (Default): Lane Numbered in
    GNT3#/      Top-Block Swap          Sampled low: Top-Block Swap mode (inverts A16 for       GLAN_DOCK#                   The pull-up or pull-down                                                    Order
    GPIO55      override. Rising Edge   all cycles targeting FWH BIOS space).                                                active when configured
                of PWROK.               Note: Software will not be able to clear the                                         for native GLAN_DOCK#           CFG10      PCIE Loopback enable 0 = Enable (Note 3)
                                                                                                                                                                                             1 = Disable (Default)
                                        Top-Swap bit until the system is rebooted                                            functionality and determined
                                        without GNT3# being pulled down.                                                     by LAN controller.              CFG[13:12] XOR/ALL                      00   =   Reserve
                                                                                                                                                                                                     10   =   XOR mode Enabled
                                                                                                                                                                                                     01   =   ALLZ mode Enable (Note 3)
    GNT0#:      Boot BIOS Destination   Controllable via Boot BIOS Destination bit              GNT[3:0]#/GPIO[55,53,51]     PULL-UP 20K                                                             11   =   Disabled (Default)
    SPI_CS1#/   Selection 0:1.          (Config Registers: Offset 3410h:bit 11:10).
    GPIO58      Rising Edge of PWROK.   GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC                    GPIO20                       PULL-DOWN 20K                   CFG16      FSB Dynamic ODT              0 = Dynamic ODT Disabled
3                                                                                               GPIO49                       PULL-UP 20K
                                                                                                                                                                                                     1 = Dynamic ODT Enabled (Default)                                                3
    SPI_MOSI    Integrated TPM Enable, Sample low: the Integrated TPM will be disable.                                                                       CFG19      DMI Lane Reversal            0 = Normal operation (Default): Lane Numbered in
                Rising Edge of CLPWROK. Sample high: the MCH TPM enable strap is sampled        LDA[3:0]#/FHW[3:0]#          PULL-UP 20K                                                                 Order
                                        low and the TPM Disable bit is clear, the                                                                                                                    1 = Reverse Lanes
                                                                                                LAN_RXD[2:0]                 PULL-UP 20K                                                             DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
                                        Integrated TPM will be enable.                                                                                                                               DMI x2 mode [MCH->ICH]: (3->0, 2->1)
                                                                                                LDRQ[0]                      PULL-UP 20K
    GPIO49      DMI Termination         The signal is required to be low for desktop                                                                         CFG20      Digital Display Port 0 = Only Digital Display Port or PCIE is
                Voltage. Rising Edge    applications and required to be high for mobile         LDRQ[1]/GPIO23               PULL-UP 20K                                (SDVO/DP/iHDMI)          operational (Default)
                of CLPWROK.             applications.                                                                                                                   Concurrent with PCIe 1 = Digital display Port the PEG port operating
                                                                                                                                                                                                 simulataneously via
                                                                                                                                                                                                                       and PCIe are
                                                                                                PME#                         PULL-UP 20K
    SATALED#    PCI Express Lane        Signal has weak internal pull-up. Sets bit 27           PWRBTN#                      PULL-UP 20K                     SDVO       SDVO Present         0 =           No SDVO Card Present (Default)
                Reversal. Rising Edge   of MPC.LR (Device 28: Function 0:Offset D8).                                                                         _CTRLDATA                       1 =           SDVO Card Present
                of PWROK.                                                                       SATALED#                     PULL-UP 15K
                                                                                                                                                             L_DDC_DATA Local Flat Panel (LFP) =
                                                                                                                                                                                             0             LFP Disabled (Default)
                                                                                                SPI_CS1#/GPIO58/CLGPIO6      PULL-UP 20K                                Present              1 =           LFP Card Present; PCIE disabled
                No Reboot.              If sampled high, the system is strapped to the
    SPKR        Rising Edge of PWROK.   "No Reboot" mode (ICH9 will disable the TCO Timer       SPI_MOSI                     PULL-DOWN 20K
                                        system reboot feature). The status is readable                                                                      NOTE:
                                                                                                SPI_MISO                     PULL-UP 20K
                                        via the NO REBOOT bit.                                                                                                1. All strap signals are sampled with respect to the leading edge of the (G)MCH
                                                                                                SPKR                         PULL-DOWN 20K                       Power OK (PWROK) signal.
                XOR Chain Entrance.     This signal should not be pull low unless using                                                                       2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of
    TP3         Rising Edge of PWROK.   XOR Chain testing.                                      TACH_[3:0]                   PULL-UP 20K
                                                                                                                                                                 the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6.
    GPIO33/     Flash Descriptor        Sampled low: the Flash Descriptor Security will be      TP[3]                        PULL-UP 20K                         Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
    HDA_DOCK    Security Override       overridden. If high, the security measures will be
2   _EN#        Strap. Rising Edge of   in effect. This should only be enabled in               USB[11:0][P,N]               PULL-DOWN 15K                                                                                                                                            2
                PWROK.                  manufacturing environments using an external
                                        pull-up resister.

           PCIE Routing page 19                            USB Table                  page 19

                                                                        USB                                                                  Thermal
                                                             Pair      Device
                                                              0        USB3                                KBC
           LANE1       LAN
                                                              1        FREE
           LANE2       MiniCard WLAN                          2        External USB3                                                         BATTERY
                                                              3        FREE
                                                              4        External USB2
                                                              5        FREE
                                                              6        WLAN
1                                                             7        BLUETOOTH                          ICH9M                                                                                                                                                                       1
                                                                                                                                                                                                                                    Wistron Corporation
                                                                                                                                                                                                                                    21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
                                                              8        CARD_READER                                                                                                                                                  Taipei Hsien 221, Taiwan, R.O.C.
                                                              9        FREE                                                                                                                  Title
                                                              10       CAMERA                                                                                                                                           Table of Content
                                                                                                                                           Clock                                             Size         Document Number                                                    Rev
                                                              11       FREE
                                                                                                                                           Generator                                         A3
                                                                                                                                                                                                                                 HBU16 1.2                                        1
                                                                                                                                                                                             Date:    Tuesday, June 30, 2009               Sheet       2        of           41

                            A                                          B                                                    C                                              D                                                                       E
                                    5                                                                                                              4                                                                                 3                                                                       2                                                                          1
         6     H_A#[35..3]

                                                                                                                                                                                                         Reserve for ITP, when
                                                             U54A 1 OF 4
                                                                                                                                                                                                         install ITP connector,
                                             H_A#3     J4                                                                                H1                         H_ADS#      6
                                                                                                                                                                                                         install R69.
                                             H_A#4           A3#                                                                ADS#
                                                       L5                                                                                E2                         H_BNR#      6
                                             H_A#5           A4#                                                                BNR#
                                                       L4    A5#                                                                BPRI#    G5                         H_BPRI#     6

                                                                                       ADDR GROUP 0
                                                                                       ADDR GROUP 0
                                             H_A#6     K5
                                             H_A#7           A6#
                                                       M3    A7#                                                           DEFER#        H5                         H_DEFER# 6
                                             H_A#8     N2                                                                                F21                                                            +1.05VS

                                                             A8#                                                            DRDY#                                   H_DRDY# 6
                                             H_A#9     J1                                                                                E1                         H_DBSY# 6
                                                             A9#                                                            DBSY#
D                                            H_A#10    N3                                                                                                                                                                                                                                                                                                                                                                     D

                                             H_A#11          A10#
                                                       P5    A11#                                                                BR0#    F1                    H_BREQ#0 6
                                             H_A#12    P2                                                                                             56R2J-4-GP                                                  R69
                                             H_A#13          A12#                                                                                                                                                 51R2F-2-GP
                                                       L2                                                                                D20 CPU_IERR# 1          2 R32 +1.05VS                          DY
                                             H_A#14          A13#                                                               IERR#
                                                       P4    A14#                                                                INIT#   B3                    H_INIT#  18
                                             H_A#15    P1

                                             H_A#16          A15#
                                                       R1    A16#                                                           LOCK#        H4                         H_LOCK#     6
                                                       M1                                                                                                                             H_CPURST#                           H_CPURST#      6
         6     H_ADSTB#0                                     ADSTB0#
         6     H_REQ#[4..0]                                                                                                              C1                                           H_RS#[2..0]   6
                                             H_REQ#0                                                                       RESET#                  H_RS#0
                                                       K3                                                                                F3
                                             H_REQ#1         REQ0#                                                           RS0#                  H_RS#1
                                                       H2    REQ1#                                                           RS1#        F4
                                             H_REQ#2   K2                                                                                G3        H_RS#2
                                             H_REQ#3         REQ2#                                                           RS2#
                                                       J3                                                                                G2                         H_TRDY#     6
                                             H_REQ#4         REQ3#                                                          TRDY#
                                                                                                                                         G6                         H_HIT#      6
                                             H_A#17                                                                              HIT#
                                                        Y2                                                                               E4                         H_HITM#     6
                                             H_A#18          A17#                                                               HITM#
                                             H_A#19          A18#                                                                                  XDP_BPM#0
                                                        R3                                                                               AD4
                                             H_A#20          A19#                                                           BPM0#                  XDP_BPM#1
                                                       W6                                                                                AD3

                                                                                                      XDP/ITP SIGNALS
                                                             A20#                                                           BPM1#
                                                             A21#                      ADDR GROUP 1
                                                                                       ADDR GROUP 1                         BPM2#
                                             H_A#23          A22#                                                           BPM3#                  XDP_BPM#4
                                                        U1                                                                               AC2
                                             H_A#24          A23#                                                           PRDY#                  XDP_BPM#5
                                                        R4   A24#                                                           PREQ#        AC1
                                             H_A#25     T5                                                                               AC5        XDP_TCK                                 H_THERMDA, H_THERMDC routing together,
                                             H_A#26          A25#                                                             TCK                  XDP_TDI
                                                        T3                                                                               AA6
                                             H_A#27    W2
                                                             A26#                                                              TDI
                                                                                                                                         AB3        XDP_TDO                                 Trace width / Spacing = 10 / 10 mil
                                             H_A#28          A27#                                                             TDO                   XDP_TMS
                                                       W5    A28#                                                             TMS        AB5
                                             H_A#29     Y4                                                                               AB6        XDP_TRST#
                                             H_A#30          A29#                                                           TRST#                   XDP_DBRESET#_R
                                                        U2                                                                               C20
                                                             A30#                                                            DBR#
C                                            H_A#31
                                                                                                                                                                                                                   CPU_PROCHOT#_R        35
                                             H_A#33          A32#
                                                             A33#                                               THERMAL
                                             H_A#34    AB2                                                                                                                             1            2                   +1.05VS
                                             H_A#35          A34#                                                                                                               R31                      68R2-GP
                                                       AA3   A35#                                                        PROCHOT#        D21
    6        H_ADSTB#1                                  V1   ADSTB1#                                                       THRMDA        A24                                                                                      H_THERMDA 24
                                                                                                                           THRMDC        B25                                                                                      H_THERMDC 24
    18        H_A20M#                                  A6
    18        H_FERR#                                  A5                                                                                C7                                   PM_THRMTRIP-A# 7,18
                                                             FERR#                                                      THERMTRIP#

    18        H_IGNNE#                                 C4
    18       H_STPCLK#                                 D5
             18     H_INTR                             C6
                                                             LINT0                                              HCLK            BCLK0
                                                                                                                                         A22                          CLK_CPU_BCLK 16
             18     H_NMI                              B4                                                                                A21                          CLK_CPU_BCLK# 16
                                                             LINT1                                                              BCLK1
                         TP4    1     RSVD_CPU_1        M4
                                                             SMI#                                                                                      PM_THRMTRIP#
                                                                                                                                                       should connect to                                                                                              +1.05VS
                                                                                                                                                                                                                                                                                                  ITP Connector
      TPAD14-GP          TP6          RSVD_CPU_2             RSVD#M4                                                                                   ICH9 and MCH
                                1                       N5
      TPAD14-GP          TP8          RSVD_CPU_3             RSVD#N5                                                                                   without T-ing
                                1                       T2

      TPAD14-GP          TP7          RSVD_CPU_4             RSVD#T2                                                                                     ( No stub)
                                1                       V3

      TPAD14-GP          TP9    1     RSVD_CPU_5        B2                                                                                                                                                                     C472                                               R293
TEST7 TPAD14-GP          TP10         RSVD_CPU_6                                                                                                                                                                               SCD47U16V2ZY-GP                                   DY

                                1                       C3   RSVD#C3
      TPAD14-GP          TP15   1     RSVD_CPU_7        D2


      TPAD14-GP          TP1          RSVD_CPU_8             RSVD#D2
      TPAD14-GP          TP14
                                                       D22   RSVD#D22                                                                                                                                                              DY                                                           ITP1
                                1                       D3

      TPAD14-GP          TP5          RSVD_CPU_10            RSVD#D3
                                1                       F6                                                                                                                                                                                                                                 29           30
                                                                                                                                                                                                    +1.05VS                                                                                 1
             TPAD14-GP   TP13   1     RSVD_CPU_11       B1                                                                                                                                                                                                                                              2                                         +1.05VS
                                                             KEY_NC                                                                                                                                                                                                              ITP_VDD                                            R277
                                                             BGA479-SKT6-GPU7                                                                                                                                                                                                               5           4        XDP_DBRESET#_R 1   DY       2 0R2J-2-GP       XDP_DBRESET#
B                                                                                                                                                                                                                                                                                           7           6        XDP_BPM#0                                                                         XDP_DBRESET# 19            B
                                                                                                                                                                                                                                                                                            9           8        XDP_BPM#1              1   DY      2 R284       0R2J-2-GP
                                                         1st: 62.10079.001                                                                                                                                                                                                                                       XDP_BPM#2                          2 R283       0R2J-2-GP                         MCH_CLKSEL2     7,16
                                                                                                                                                                                                                                                                                           11           10                              1   DY                                                     MCH_CLKSEL1     7,16
                                                         2nd: 62.10053.401                                                                                                                                                                                                                 13           12       XDP_BPM#3
                                                                                                                                                                                                                                                                                                                                        1   DY      2 R282       0R2J-2-GP

◦ Jabse Service Manual Search 2019 ◦ Jabse Pravopis ◦ Other service manual resources online : FixyaeServiceinfo