Service Manuals, User Guides, Schematic Diagrams or docs for : Compaq-HP HPCQ43 FOXCONNCHICAGO MONTEVINAUMA
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5 4 3 2 1
D
TABLE OF CONTENTS D
MB
P01 : COVER SHEET P24 : Cantiga (GRAPHIC) 3/7
P02 : SYSTEM BLOCK DIAGRAM P25 : Cantiga (DDR3) 4/7
P03 : POWER MAP P26 : Cantiga (POWER,VCC) 5/7
P04 : POWER SEQUENCY DIAGRAM P27 : Cantiga (VCC CORE) 6/7
P05 : CLOCK MAP P28 : Cantiga (VSS) 7/7
P06 : SMBUS&I2C MAP P29 : ICH9-M (PCI/USB) 1/5
C P07 : POWER SEQUENCE P30 : ICH9-M(LPC,IDE,SATA) 2/5 C
P08 : DCIN/BATT P31 : ICH9-M (GPIO) 3/5
P09 : PWR_CHARGE P32 : ICH9-M (POWER) 4/5
P10 : PWR_5V/3.3V P33 : ICH9-M (GND) 5/5
P11 : PWR_VTT P34 : DDR3(SO-DIMM_0) 1/2
P12 : PWR_1.5V/0.75S P35 : DDR3(SO-DIMM_1) 2/2
P13 : PWR_CPU_VCORE P36 : CLOCK GEN
P14 : PWR_OTHER P37 : EC+KBC (IT8518)
P15 : PWR_(Empty) P38 : Audio(CODEC)
B
P16 : PWR_1.8VS P39 : Audio(JACK/SPEAKER/MIC) B
P17 : PWR_(Empty) P40 : LAN (RTL8165EH)
P18 : POWER SEQUENCY CHART P41 : Card Reader(RTL5219)
P19 : Penryn(HOST BUS)1/3 P42 : Mini PCIe&BT/PWRB/Control
P20 : Penryn(HOST BUS)2/3 P43 : USBX2/USB DB/SATA CONN
P21 : Penryn(Power/Gnd)3/3 P44 : LVDS/Webcam
P22 : Cantiga (HOST) 1/7 P45 : HDMI & CRT P. Leader Check by Design by
P23 : Cantiga (DMI) 2/7 P46 : Thermal/Fan/Stitch Cap
A A
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
Index Page
Size Document Number Rev
Custom 0.1
TPN-F101/TPN-F102 Montevina p
Page Modified: Monday, January 24, 2011 08:43:01 (UTC/GMT) Sheet 1 of 46
5 4 3 2 1
1 2 3 4 5 6 7 8
Intel
CLK Gen
Montevina RealTek
(Penryn) ICS9LPRS397DKLFT
P27
A (TPD:35W) A
HDMI Level Shifter
Conn. ESD FSB
667/800/1066 MHz X,TAL
14.318MHZ
SO-DIMM 0
CRT Buffer 800 MHZ Supports up to 800 MHZ
Conn. ESD DDR(III)
North Bridge
LVDS GL40 SO-DIMM 1
800 MHZ Supports up to 800 MHZ
Conn.
DDR(III)
DMI X4 LAN
Realtek Transformer
PCIe(100MHz) RJ45
B
RTL8165EH Conn. P.??
B
(10/100) P.??
P.??
South Bridge
ICH9-M SATA(100MHz) SATA : HDD
Int. Speaker x2 P.??
Digital Mic x1 CODEC
RealTek HDA SATA(100MHz) SATA : ODD
Ext. Mic In Jack
ALC270A-GR (USB x 11)
Headphone Jack
(PCIE x 6)
BGA-676 (SATA x 2) PCIe(100MHz) MiniCard Slot 1
USB 2.0 WLAN/BT
USB 2.0
USB 2.0 Standard Port x1 P.??
C C
USB 2.0 PCIe(100MHz) CardReader 2-IN-1
USB 2.0 Standard Port x1 P.??
x2 Controller Combo
RTS5219 Connector
USB 2.0
Webcam x1
SPI BIOS ROM
4MB P.??
LPC
PWM KBMX Keyboard
FAN
Thermal sense
Embedded PS/2
SMBUS Touch PAD
G781-1P8F Controller
D D
SPI
(ITE_IT8518) GPIO Power Button
KBC ROM
Lid switch Hon Hai Precision Industry Co. Ltd.
512KB Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
SYSTEM BLOCK DIAGRAM
Size Document Number Rev
Custom TPN-F101/TPN-F102 0.1
Montevina platform
Page Modified: Monday, January 24, 2011 08:43:02 (UTC/GMT) Sheet 2 of 46
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
POWER MAP
+V5A
+VBAT
TI (5.6A)
Adaptor TPS51125A IRF8707 +V5S
SLP_S3#_3R (2.8A)
19.5V EC_ALW_EN
For +V5A
+VAL
ENTRIP1
(0.1A)
65W PGOOD
+V3.3A
TI (4.8A)
4.6A
TPS51125A IRF8707 +V3.3S
SLP_S3#_3R (3.3A)
For +V5A
ENTRIP2
C EN0 C
+V3AL
+VBAT +VCC_CORE (22A/44A Peak)
IMVP_VR_ON_PWR IMVP_PWRGD
Battery EN ADP3208D
Charger
O2 OZ8681LN
Charging
Current
+VBAT +VTT
SLP_S3#_3R_PWR
TPS51218 VTT_PG
(12A)
EN PGOOD
PM_SLP_A#
LDO +V0.75S
B B
+V5S UP7711 (1.0A)
+VBAT
+V1.5
TPS51218 (10A)
SLP_S4#_3R V1,5_PG
EN PGOOD IRF8707 +V1.5_VDDQ
Battery SLP_S3#_3R (6.0A)
Pack +VBAT +V1.8S
3S2P +V5S
UP7711 (7.0A)
EN
A A
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
History
Size Document Number Rev
Custom TPN-F101/TPN-F102 Montevin
0.1
Page Modified: Monday, January 24, 2011 08:43:03 (UTC/GMT) Sheet 3 of 46
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5 4 3 2 1
D D
+V5A
+VBAT
+V3.3AL
2
TPS51125ARGER +V3.3A
EC_ALW_EN
1
ALL_SYS_PWRGD
EC
ITE8518
C
EC_PWRBTN# 2 +VBAT C
DDR_PG
PWRGD 4
+V1.5
ICH9-M
SLP_S4#_3R 3 4
SLP_S3#_3R 5 TPS51218DSCR
+VBAT
+VTT SLP_S3#_3R
7
6 AND ALL_SYS_PWRGD
5 SLP_S3#_3R
TPS51218DSCR
VTT_PG
PWRGD 6
5
+V1.5
+V0.75S
+V5A
SWITCH 6
+V5S
uP7711U8 7
+V5S
+V3.3A SLP_S3#_3R Q1404 +V3.3S
EN
Q1405 6
+V3.3S
+V1.5
Q1406 6
+V1.5_VDDQ +V1.8S
uP7711U8 7
+V5S
EN
B B
+VCC_CORE
IMVP_VR_ON
8 9 SLP_S3#_3R 10
ADP3208DJCPZ AND PCH_PWROK
PWRGD 9 VR_PWRGD
Power on Sequence required:
GL40:
1, +V3.3A ramp before +V1.1A
2, +V3.3S ramp before +V1.8S
3, +V1.8S ramp before +V1.1S
4, +V3.3S ramp before +V1.1S
ICH9-M:
1, 0 <(+V3.3S) - (+V1.8S) < 2.1
2, +V1.8S ramp before +V1.1S
3. +V1.1S ramp before VCC_NB
A A
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
POWER SEQUENCY DIAGRAM
Size Document Number Rev
Custom 0.1
TPN-F101/TPN-F102 Montevina
Page Modified: Monday, January 24, 2011 08:43:03 (UTC/GMT) Sheet 4 of 46
5 4 3 2 1
5 4 3 2 1
71 CLK_CPUBCLK A22
BCLK[0]
CPU
(166/200/266MHz) 70 CLK_CPUBCLK# A21
BCLK[1] Penryn
D 64 CLK_XDP 40 D
(166/200/266MHz) 63 CLK_XDP# 42 XDP Connector
AP24 SDDR_A_CLK_DDR0
(166/200/266MHz)
68 CLK_MCHBCLK AH7 HPLL_CLK GMCH AR24 SDDR_A_CLK_DDR0# DDRIII
67 CLK_MCHBCLK# AH6 HPLL_CLK#
61 CLK_PEG_MCH F43 PEG_CLK
GL40 AT21 SDDR_A_CLK_DDR1 SO-DIMM Slot A
AR21 SDDR_A_CLK_DDR1#
(100MHz) 60 CLK_PEG_MCH# E43 PEG_CLK#
24 CLK_DREF B38 DPLL_REF_CLK
AV24 SDDR_B_CLK_DDR0
(96MHz) 25 CLK_DREF# A38 DPLL_REF_CLK#
AU24 SDDR_B_CLK_DDR0# DDRIII
28 SSCLK1_DREF E41 AU20 SDDR_B_CLK_DDR1 SO-DIMM Slot B
DPLL_REF_SSCLK
(100MHz) 29 SSCLK1_DREF# F41 AV20 SDDR_B_CLK_DDR1#
C DPLL_REF_SSCLK# C
35 CLK_PCIE_ICH T25 DMI_CLKP
(100MHz) 36 CLK_PCIE_ICH# T26 DMI_CLKN
ICH9-M
32 CLK_SATA1 AJ18 SATA_CLKP
(100MHz) 33 CLK_SATA1# AH18 SATA_CLKN
20 CLK_R3S_ICH48 AF3
(48MHz) CLK48
C23
20 CLK_R3S_ICHPCI D4
(33MHz) PCICLK 32.768kHz Crystal
8 CLK_R3S_ICH14 H1 C24
(14.318MHz) CLK14
B 50 CLK_PCH_PCIE_CR 3 B
(100MHz) 51 CLK_PCH_PCIE_CR# 4 CardReader RTS5219-GR
44 CLK_PCH_PCIE_LAN 19
(100MHz) 45 CLK_PCH_PCIE_LAN# 20 LAN RTL8165EH-CG
48 CLK_PCH_PCIE_MINI 13
(100MHz) 47 CLK_PCH_PCIE_MINI# 11
19
Half Mini Card WLAN/BT
16 CLK_PCI_JIG 14
(33MHz)
DEBUG CARD Connector
15 CLK_R3S_KBPCI 13
(33MHz) KBC ITE8518
A A
4
EC_SPI_CLK Hon Hai Precision Industry Co. Ltd.
(14.318MHz) 14.318MHz Crystal Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
5
CK505 32.768kHz Crystal SPI ROM Title
CLOCK MAP
ICS9LPRS397DKLFT Size Document Number
0.1
Rev
Custom TPN-F101/TPN-F102 Montevina p
Page Modified: Monday, January 24, 2011 08:43:01 (UTC/GMT) Sheet 5 of 46
5 4 3 2 1
5 4 3 2 1
D D
+V3.3A +V3.3S
+V5S
4.7K ohm ICH_3S_SMCLK 4.7K ohm
ICH_3S_SMDATA
DIMM0
ICH_3A_SMDATA
2N7002
ICH_3A_SMCLK
C C
DIMM1
+V5S_SYNC +V3.3S
2.2K ohm 2.2K ohm
CLOCK
SMBDATA
SMBCLK
CRT_DDC_DATA_5S CRT_DDC_DATA UCRT_DDC_DATA
CRT_DDC_CLK_5S Buffer CRT_DDC_CLK UCRT_DDC_CLK CRT_DDC_DATA
CRT Level Shift CRT_DDC_CLK
GEN
ESD +V3.3S
2.2K ohm
LVDS_DDC_DATA ULVDS_DDC_DATA WLAN
LVDS_DDC_CLK ULVDS_DDC_CLK L_DDC_DATA
LVDS L_DDC_CLK
+V5S +V3.3S
GMCH ICH9-M
2.2K ohm 2.2K ohm
HDMI_DDC_DATA UTMDS_DDC_DATA
B B
HDMI_DDC_CLK Level UTMDS_DDC_CLK SDVO_CTRLDATA
HDMI Shifter SDVO_CTRLCLK
+V3.3S +V3.3AL
+V3.3S
4.7K ohm 2.2K ohm
Temp Sensor_1
2N7002 SMDAT0 SMDAT2
( For GPU ) EC_SMB0_DAT_3S EC_SMB0_DAT_3AL SMCLK0 SMCLK2
EC_SMB0_CLK_3S EC_SMB0_CLK_3AL
Temp Sensor_2 EC
+V3.3AL
( For CPU ) Charger 2.2K ohm ITE8502
EC_SMB1_DAT_3AL
A A
EC_SMB1_CLK_3AL
SMDAT1
Battery SMCLK1
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
Title
SMBUS&I2C MAP
Size Document Number Rev
Custom 0.1
TPN-F101/TPN-F102 Montevina p
Page Modified: Monday, January 24, 2011 08:43:01 (UTC/GMT) Sheet 6 of 46
5 4 3 2 1
5 4 3 2 1
Power on Sequence required:
D D
ICH9M:
H_CPU_RST# 1, +V3.3A ramp before +V1.1A
(NB to CPU) 2, +V3.3S ramp before +V1.8S
3, +V1.8S ramp before +V1.1S
PLT_RST# 5, +V3.3A ramping down time > 300us
(SB to NB) 6, 50uS <= All power rails except +V3.3A <= 40mS
7, 100uS <= +V3.3A <= 40mS
RC=~99ms
PCH_PWROK GMCH:
1, 0 <(+V3.3S) - (+V1.8S) < 2.1
2, +V1.8S ramp before +V1.1S
VR_PWRGD RC=0 RC=0 3. +V1.1S ramp before +VCC_NB
+VCC_CORE
218.232ms
IMVP_VR_ON 0.8V - 1.1V
CLK running
RC=0
2.323ms
CK_PWGD 0.9V
-172.922us
ALL_SYS_PWRGD
C C
+VTT_PG 1.994ms
+VTT 1.05V 626.011us
+V0.75S only will be shut down in S3 mode
+V0.75S/M_VREF 29.072ms
+V1.8S 3.207ms
+V1.5_VDDQ 1.730ms
+V3.3S 2.300ms
+V5S 2.174ms
to S3
217.609ms
SLP_S3#_3R (SB to EC)
2.134ms
DDR_PG
687.574us
B
+V1.5 B
329.263ms
SLP_S5#_3R,SLP_S4#_3R
(SB to EC)
Power button from EC to SB
EC_PWRBTN#
20.3424ms
RSMRST# (EC to SB)
+V12A
+V12A When IMC, always on at all time( always PWR)
3.118ms
+V3.3A
+V3.3A When IMC, always on at all time( always PWR)
5.148ms
+V5A
When IMC, always on at all time( always PWR)
+V5A 2.856ms
EC_ALW_EN (from EC)
Power button pressed
A PWR_SWIN# A
AC not present scenario = LOW AC present= high
ACPRES
(ACIN detect)
+V5AL/+V3.3AL
Hon Hai Precision Industry Co. Ltd.
Foxconn eMS Inc.
Battery inserted/AC IN 8807 Fallbrook Drive phone: +886-2-2799-6111
+VBAT HNBD R&D fax: (281) 668-1515
Title
POWER SEQUENCE
+VCC_RTC
Size Document Number Rev
Custom
TPN-F101/TPN-F102 Montevina platform 0.1
Page Modified: Monday, January 24, 2011 08:43:03 (UTC/GMT) Sheet 7 of 46
5 4 3 2 1
A B C D E
DC_JACK WIRE to BOARD CONNECTOR
4 4
CON0801
HEADER_1X7_DCIN DCIN_CON 1 2
I DCIN
JP0801
1 NI
2
2 C0801 C0802
3 D0801 100nF_X7R_25V 1nF_X7R_25V
4 PESD24VS1UL 0402
5 0603
SOD882-2
1
6 I
NI I
7
SMART_ADP_ID
+V3.3A
+V3.3A
R0802
C0803 130K_1%
Modify 10/21 R0803 0402 U0801 R0801
10nF_X7R_25V
R0806 75K_1% I TS391CG-AF5-R 100K_5%
5
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