Service Manuals, User Guides, Schematic Diagrams or docs for : Compaq-HP HP_CQ42_AX1 INTEL UMA DISCRETE
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>> Download HP_CQ42_AX1 INTEL UMA DISCRETE documenatation <<
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AX1 INTEL UMA/DISCRETE SYSTEM DIAGRAM 14.318MHz
+3V/+5V CLOCK GEN
A PG.2 A
PG.32
+1.05V/+1.8V SODIMM1 DDR3 INTEL
Max. 4GB
PG.33
PG.12
Channel A
Arrandale AMD
CPU Core PCI-E x16 PARK-LP HDMI
37.5mm X 37.5mm HDMI PG.21
PG.34 SODIMM2 DDR3 989pin PGA 23mm X 23mm
VGA Core/+1.1V Max. 4GB CRT CRT
PG.13
Channel B TDP 35W TDP 8W PG.22
PG.36 LVDS
PG.3~6 PG.14~18 LVDS PG.20
+1.5VSUS DDR3 700MHz
FDI DMI
B
PG.37 VRAM B
+1.05VTT 64Mx16x4,64bit PG.19
HDMI
SATA0 Level
PG.35 HDD PG.23
UMA VGACORE Shifter
PG.21
SATA1
PG.40
ODD PG.23
INTEL PCH DP Port B
Charger
PG.39
Ibex Peak-m CRT
LVDS
PCI-E x 1
27mm X 25mm
LANE1 LANEO
1071pin FCBGA USB2.0 Ports Webcam
C
LAN WLAN USB 2.0 TDP 5W X2
C
RTL8103EL-VB-GR BT COMBO PORT10 PG.26 PG.20
10/100 PG.27 PG.31 USB 2.0 PORT0,1 PORT2
PORT4 PORT5
LPC
Card Reader BT Stackup
KBC PG.7~11 RTS5159-GR Softbreeze
EnE KB3926QF D2 PG.29 PG.24 PG.26
TOP
GND
KB TP ROM FAN Azalia IN1
Speaker IN2
PG.25
D
Modem AUDIO VCC D
CODEC HP/MIC BOT
PG.26
RJ-11 ALC270-GR PROJECT :AX1
Analog MIC Quanta Computer Inc.
PG.26 PG.25 PG.25
Size Document Number Rev
Custom 1A
BLOCK DIAGRAM
Date: Wednesday, July 08, 2009 Sheet 1 of 40
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
25mA 150mA 150mA
02
+3V +VDDCORE_CLK Y1
+1.05V +VDDIO_CLK +3V +VDDSE_CLK L35 XTAL_IN 1 2XTAL_OUT +3V
L33 L37 1 2 C425 4.7U/6.3V_6
1 2 C454 0.1U/10V_4 1 2 C469 4.7U/6.3V_6 *HCB1608KF-181T15_6
14.318MHZ
1
1
HCB1608KF-181T15_6 C436 0.1U/10V_4 HCB1608KF-181T15_6 C465 0.1U/10V_4 +1.5V C435 0.1U/10V_4
C423 10U/6.3V_6S C480 0.1U/10V_4 L34 C481 0.1U/10V_4 C460 C455 R298
A A
C442 *10U/6.3V_8S 1 2 C437 0.1U/10V_4 33P/50V_4 33P/50V_4 *10K/F_4
2
2
HCB1608KF-181T15_6
Place each 0.1uF cap close to pin Place each 0.1uF cap close to pin Place each 0.1uF cap close to pin CPU_SEL
R300
10K/F_4
0 1
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz
(default)
U13
+VDDSE_CLK 5 23 CLK_BUF_BCLK_P RP24 4 3 *4P2R-S-0 CLK_BUF_BCLK_P <8>
VDD_LCD CPU-0 CLK_BUF_BCLK_N
29 VDD_REF CPU-0# 22 2 1 CLK_BUF_BCLK_N <8>
+VDDCORE_CLK 1 VDD_USB CPU-1 20
2 1 17 VDD_SRC CPU-1# 19
C482 *0.047U/10V 24
+VDDIO_CLK 18
VDD_CPU
9LRS3197 3 CLK_BUF_DREFCLK RP27 2 1 *4P2R-S-0 CLK_BUF_DREFCLK <8>
+3V
VDD_CPU_IO DOT96T_LPR CLK_BUF_DREFCLK#
B 2 1 15 VDD_SRC_IO DOT96C_LPR 4 4 3 CLK_BUF_DREFCLK# <8> B
C415 *0.047U/10V
<8,12,13> CGDAT_SMB 31 13 CLK_BUF_PCIE_3GPLL RP25 2 1 *4P2R-S-0 CLK_BUF_PCIE_3GPLL <8>
SDATA SRC-1 CLK_BUF_PCIE_3GPLL# R282
<8,12,13> CGCLK_SMB 32 SCLK SRC-1# 14 4 3 CLK_BUF_PCIE_3GPLL# <8>
1K/F_4
+3V R279 10K/F_4 16 10 CLK_BUF_DREFSSCLK RP26 2 1 *4P2R-S-0 CLK_BUF_DREFSSCLK <8>
CLK_ICH_14M R293 33_4 CPU_SEL CPU_STOP# SATA CLK_BUF_DREFSSCLK#
<8> CLK_ICH_14M 30 REF_0/CPU_SEL SATA# 11 4 3 CLK_BUF_DREFSSCLK# <8>
C477 *10P/50V_4 CK_PWRGD_R
CK_PWRGD_R 25 6 CLK_VGA_27M_NOSS R304 22_4 EVGA-XTALI <15>
CK_PW RGD/PD#_3.3 27MHz_nonSS R494 22_4
Place R8044 within 0.5" of C/G 27MHz_SS 7 0918 SI Modify 27M_TCK <15>
3
XTAL_OUT 27 Q15
XTAL_IN XOUT CLK_VGA_27M_SS R303 *33_4 2N7002E
28 33
9
XIN
VSS_SATA
QFN32 GND
VSS_REF 26
CLK_27M_SS <15>
R280
2 VSS_USB VSS_CPU 21 Discrete only <34> VR_PWRGD_CLKEN# 2 100K/F_4
8 VSS_LCD VSS_SRC 12
9LRS3197
1
+3V
EMI request
+1.05V
C812 .1U/10V_4
C813 .1U/10V_4
C814 .1U/10V_4
C815 .1U/10V_4
C816 .1U/10V_4
C817 .1U/10V_4
C818 .1U/10V_4
C819 .1U/10V_4
C820 .1U/10V_4
C821 .1U/10V_4
C C
+1.05V <7,8,9,11,13,33,34,40>
+1.5V <31,38>
+3V <3,7,8,9,10,11,12,13,15,20,21,22,23,24,25,26,27,28,29,30,31,34,38>
CPU GPU PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8
H6 H4 H3 H11
*H-TC248BC197D150P2
*H-TC248BC197D150P2
*H-TC248BC197D150P2
*H-TC248BC197D150P2
*H-TC248BC197D150P2
H10 H9 H0 H1 H2 H5 H7 H8
*H-TC248BC197D150P2
*H-TC248BC197D150P2
*h-c354d118p2
*h-c236d118p2
*h-c236d118p2
*h-c354d118p2
*h-c276d118p2
*h-c354d118p2
*h-c354d118p2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D H12 H18 D
*h-c354d118p2
H13 H16 H17
*H-c354d354n
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