Service Manuals, User Guides, Schematic Diagrams or docs for : Compaq-HP NC6400 Compal LA-2952P
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A B C D E
1 1
2
Compal confidential 2
Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_P/GM+ ICH7-M core logic
3
2005-10-26 3
REV:0.3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2952P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2005 Sheet 1 of 46
A B C D E
A B C D E
Compal confidential
File Name : LA-2952P
Caymus
1 1
Fan Control Accelerometer
page 4
Mobile Yonah/Merom Thermal Sensor Clock Generator LIS3LV02DQ
uFCPGA-478 CPU ADM1032AR ICS9LP306BGLFT
page 24
page 4,5,6 page 4 page 15
CRT / TV-OUT
page 16 FSB
H_A#(3..31) 533/667MHz H_D#(0..63)
DDR2 -400/533/667 DDR2-SO-DIMM X2
LCD CONN BANK 0, 1, 2, 3 page 13,14
page 17
Intel Calistoga MCH Dual Channel
DVI 945GM USB conn x2
CH7307C PCBGA 1466 (Docking) page 32
page 7,8,9,10,11,12
page 16 FingerPrinter AES2501
2
USBx1 page 29 daughter board 2
USB2.0
USB conn x3
DMI page 27
PCI-E BUS BT Conn
page 27
PCI BUS Mini-Card WWAN
page 24
AC-LINK/Azalia
daughter board Intel ICH7-M MDC
page 31
Mini-Card Audio CKT
CardBus Controller mBGA-652 AD1981HD page 25 AMP & Audio Jack
10/100/1000 LAN WLAN MAX9710 page 26
LED BCM5753M page 24 TI PCI6612 page 18,19,20,21 SATA
page 29 page 22/23 SATA HDD Connector
3 3
SPI page 19 Docking CONN.
SPI ROM PATA Slave
*RJ-45(LED*2)
RTC CKT. Slot 0/Smart Card SD/MMC Slot Multi-bay II Connector *RJ-11(Pass Through)
page 19
RJ45/11 CONN 25LF080A
page 29 page 19 *CRT
page 23
*COMPOSITE Video Out
LPC BUS *TVOUT
*DVI
Power OK CKT. *LINE IN
page 34 *LINE OUT
*PCI-E x2
TPM 1.2 SMSC Super I/O *Serial Port
Power On/Off CKT. SMSC KBC 1021 LPC47N217 34
*Parallel Port
page 29 page 30 page *PS/2 x2
page 31 *USB x2
*DC JACK
Int.KBD COM1 LPT
page 34
4 DC/DC Interface CKT. Touch Pad CONN. ( Docking ) ( Docking ) 4
page 31 page 37 page 32 page 32
page 33
Power Circuit DC/DC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
Page 35,36,37,38,39,40,41,42,43 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2952P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2005 Sheet 2 of 46
A B C D E
5 4 3 2 1
Symbol Note :
Voltage Rails
Power Plane Description S0-S1 S3 S5
: means Digital Ground
VIN Adapter power supply (18.5V) N/A N/A N/A
D
B+ AC or battery power rail for power circuit N/A N/A N/A : means Analog Ground D
+CPU_CORE Core voltage for CPU ON OFF OFF
+VCCP 1.05V power rail for Processor I/O and MCH/ICH core power ON OFF OFF
+0.9VS 0.9V switched power rail for DDRII Vtt ON OFF OFF
+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF
@ : means just reserve , no build
+1.8V 1.8V power rail for DDRII ON ON OFF
M52@ : means build discrete sku with ATI VGA M52 .
+1.8VS 1.8V switched power rail ON OFF OFF
UMA@ : means build UMA sku with Intel 945GM .
SPI@ : means just build when SPI I/F BIOS function reserve.
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF FWH@ : means just build when FWH I/F BIOS function reserve.
+3VALW 3.3V always on power rail ON ON ON* NOXDP@ : means just build when XDP function disable.
+3VS 3.3V switched power rail ON OFF OFF XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
1021@ : means just build when SMsC KBC1021 chip selected.
+RTC_VCC RTC power ON ON ON
LP@ : means just build when Low power clock gen. install
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
NOLP@ : means just build when Low power clock gen. NO install
C C
45@ : means need be mounted when 45 level assy or rework stage.
Internal PCI Devices
DEVICE Bus PCI Device ID IDSEL #
LAN 1 D8 AD24
Azalia 0 D27 AD11
PCI-E 0 D28 AD12
USB1.1/2.0 0 D29 AD13
PCI to PCI (DMI to PCI) 0 D30 AD14
AC97 MODEM 0 D30 AD14
AC97 Audio 0 D30 AD14
PATA/SATA 0 D31 AD15
LPC I/F 0 D31 AD15
SMBUS 0 D31 AD15
CPU I/F 0 D31 AD15
B
DMA 0 D31 AD15 B
PMU 0 D31 AD15
External PCI Devices
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
CARD BUS D6 AD22 2 CDEG
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0 A0 10100000
A
DDR SO-DIMM 1 A4 10100100 A
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2952P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2005 Sheet 3 of 46
5 4 3 2 1
5 4 3 2 1
+3VS
<7> H_A#[3..31] H_D#[0..63] <7>
JP12A
R1294
H_A#3 J4 E22 H_D#0 XDP_DBRESET#_R 1 2 @ 1K_0402_5%
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
ITP-XDP Connector +VCCP
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 This shall place near CPU
M1 A7# D4# F23
H_A#8 N2 G25 H_D#5 JP19 XDP_TDI R246 1 2 56_0402_5%
H_A#9 A8# D5# H_D#6
J1 A9# D6# E25 1 GND0 GND1 2
D H_A#10 H_D#7 XDP_BPM#5 XDP_TMS R236 1 56_0402_1% D
N3 A10# D7# E23 3 OBSFN_A0 OBSFN_C0 4 2
H_A#11 P5 K24 H_D#8 XDP_BPM#4 5 6 XDP_TDO R238 1 2 56_0402_5%
H_A#12 A11# D8# H_D#9 OBSFN_A1 OBSFN_C1
P2 A12# D9# G24 7 GND2 GND3 8
H_A#13 L1 J24 H_D#10 XDP_BPM#3 9 10 XDP_BPM#5 R241 1 2 56_0402_5%
H_A#14 A13# D10# H_D#11 XDP_BPM#2 OBSDATA_A0 OBSDATA_C0
P4 A14# D11# J23 11 OBSDATA_A1 OBSDATA_C1 12
H_A#15 P1 H26 H_D#12 13 14 XDP_TRST# R237 1 2 56_0402_5%
H_A#16 A15# D12# H_D#13 XDP_BPM#1 GND4 GND5
R1 A16# D13# F26 15 OBSDATA_A2 OBSDATA_C2 16
H_A#17 Y2 K22 H_D#14 XDP_BPM#0 17 18 XDP_TCK R239 1 2 56_0402_5%
H_A#18 A17# D14# H_D#15 OBSDATA_A3 OBSDATA_C3
U5 A18# D15# H25 19 GND6 GND7 20
H_A#19 R3 N22 H_D#16 21 22
H_A#20 A19# D16# H_D#17 OBSFN_B0 OBSFN_D0
W6 A20# D17# K25 23 OBSFN_B1 OBSFN_D1 24
H_A#21 U4 P26 H_D#18 25 26
H_A#22 A21# D18# H_D#19 GND8 GND9
Y5 A22# D19# R23 27 OBSDATA_B0 OBSDATA_D0 28
H_A#23 U2 L25 H_D#20 29 30
H_A#24 A23# D20# H_D#21 OBSDATA_B1 OBSDATA_D1
R4 A24# D21# L22 31 GND10 GND11 32
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 33 34
H_A#26 A25# D22# H_D#23 OBSDATA_B2 OBSDATA_D2
T3 A26# D23# M23 35 OBSDATA_B3 OBSDATA_D3 36
H_A#27 W3 P25 H_D#24 R1295 37 38
H_A#28 A27# D24# H_D#25 H_PWRGOOD 2 GND12 GND13
W5 A28# D25# P22 1H_PWRGOOD_R 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_CPU_XDP CLK_CPU_XDP <15>
H_A#29 Y4 P23 H_D#26 1K_0402_5% 41 42 CLK_CPU_XDP# CLK_CPU_XDP# <15>
H_A#30 A29# D26# H_D#27 HOOK1 ITPCLK#/HOOK5
W2 A30# D27# T24 +VCCP 43 VCC_OBS_AB VCC_OBS_CD 44 +VCCP 1K_0402_1%
H_A#31 Y1 R24 H_D#28 2 1 45 46 H_RESET#_R 1 R242 2 H_RESET#
<7> H_REQ#[0..4] A31# D28# HOOK2 RESET#/HOOK6
L26 H_D#29 C948 0.1U_0402_16V4Z 47 48 XDP_DBRESET#_R 2 R243 1 XDP_DBRESET#
H_REQ#0 D29# H_D#30 HOOK3 DBR#/HOOK7 200_0402_1%
K3 REQ0# D30# T25 49 GND14 GND15 50
H_REQ#1 H2 N24 H_D#31 ICH_SMBDATA 51 52 XDP_TDO
H_REQ#2 REQ1# D31# H_D#32 ICH_SMBCLK SDA TD0 XDP_TRST#
K2 REQ2# D32# AA23 53 SCL TRST# 54
H_REQ#3 J3 AB24 H_D#33 55 56 XDP_TDI
H_REQ#4 REQ3# D33# H_D#34 XDP_TCK TCK1 TDI XDP_TMS
L5 REQ4# D34# V24 57 TCK0 TMS 58
V26 H_D#35 59 60 XDP_PRE 1 R1296 2 0_0402_5%
H_ADSTB#0 D35# H_D#36 GND16 GND17
<7> H_ADSTB#0 L2 ADSTB0# D36# W25
H_ADSTB#1 V4 U23 H_D#37 SAMTE_BSH-030-01-L-D-A
<7> H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 C
D39# U22
AB25 H_D#40
D40# H_D#41
D41# W22
Y23 H_D#42
CLK_CPU_BCLK D42# H_D#43
<15> CLK_CPU_BCLK A22 BCLK0 D43# AA26
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45
Y22
D45#
D46# AC26
AA24
H_D#46
H_D#47
Thermal Sensor ADM1032AR-2
H_ADS# D47# H_D#48
<7> H_ADS# H1 ADS# D48# AC22
H_BNR# E2 AC23 H_D#49 +3VS
<7> H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52 2
<7> H_DEFER# DEFER# D52#
H_DRDY# F21 AC25 H_D#53 C273
<7> H_DRDY# DRDY# D53#
R172 H_HIT# G6 AD20 H_D#54
<7> H_HIT# HIT# D54#
1
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55 0.1U_0402_16V4Z
<7> H_HITM# HITM# D55# 1
1 2 H_IERR# D20 AF23 H_D#56 R227
+VCCP H_LOCK# IERR# D56# H_D#57 U16
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58 1 8 ICH_SMBCLK 10K_0402_5%
<7> H_RESET# RESET# D58# VDD SCLK
AD21 H_D#59
2
D59# H_D#60 H_THERMDA ICH_SMBDATA
<7> H_RS#[0..2] D60# AE25 2 D+ SDATA 7
H_RS#0 F3 AF25 H_D#61 C264
H_RS#1 RS0# D61# H_D#62 H_THERMDC THERM_SCI#
F4 RS1# D62# AF22 1 2 3 D- ALERT# 6 THERM_SCI# <20>
H_RS#2 G3 AF26 H_D#63
H_TRDY# RS2# D63# 2200P_0402_50V7K THERM#
<7> H_TRDY# G2 TRDY# 4 THERM# GND 5
J26 H_DINV#0 R228
DINV0# H_DINV#0 <7>
M26 H_DINV#1 +3VS 1 2 ADM1032AR-2_MSOP8
DINV1# H_DINV#1 <7>
XDP_BPM#0 AD4 V23 H_DINV#2
BPM0# DINV2# H_DINV#2 <7>
XDP_BPM#1 AD3 AC20 H_DINV#3 10K_0402_5% Address:1001_101
BPM1# DINV3# H_DINV#3 <7>
XDP_BPM#2 AD1
B XDP_BPM#3 BPM2# ICH_SMBCLK B
AC4 BPM3# H_DSTBN#[0..3] <7> <13,14,15,20,22,24> ICH_SMBCLK
H23 H_DSTBN#0 ICH_SMBDATA
DSTBN0# <13,14,15,20,22,24> ICH_SMBDATA
<20> XDP_DBRESET# XDP_DBRESET# C20 M24 H_DSTBN#1
H_DBSY# DBR# DSTBN1# H_DSTBN#2
<7> H_DBSY# E1 DBSY# DSTBN2# W24
H_DPSLP# B5 AD23 H_DSTBN#3
<19> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0
<19,42> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
<7> H_DPWR# DPWR# DSTBP1#
XDP_BPM#4 AC2 MISC Y25 H_DSTBP#2
<42> H_PROCHOT# PRDY# DSTBP2# +5VS
XDP_BPM#5 AC1 AE24 H_DSTBP#3
+VCCP 1 R410 2
56_0402_5%
H_PROCHOT# D21 PREQ#
PROCHOT#
DSTBP3#
PWM Fan Control circuit
<19> H_PWRGOOD H_PWRGOOD D6
H_CPUSLP# PWRGOOD JP8
<7> H_CPUSLP# D7 SLP#
1
XDP_TCK AC5 1 1
XDP_TDI TCK H_A20M# D11 C122 C125 1
AA6 TDI A20M# A6 H_A20M# <19> 2
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