Service Manuals, User Guides, Schematic Diagrams or docs for : Compaq-HP dv4 LA-4117P
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A B C D E
1 1
2
Compal confidential 2
Schematics Document
Mobile AMD S1G3 CPU with ATI
3
RS880M(NB) & SB710(SB) core logic 3
2009-03-15
REV:0.3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 1 of 56
A B C D E
A B C D E
Compal Confidential
Consumer AMD 14" UMA - Ripley 2.0 (NBW20)
Accelerometer Thermal Sensor
72QFN
1
ST LIS302DLTR ADM1032ARMZ AMD S1G3 CPU DDR2-SO-DIMM X2 1
Page 30 Page 6 DDR2 800MHz 1.8V BANK 0, 1, 2, 3 Page 8, 9 Clock Generator
Dual Channel SLG8SP626VTR
Fan conn
638-PIN uFCPGA 638 Page 15
Page 4
Page 4, 5, 6, 7
Side-Port DDR2 SDRAM
Hyper Transport Link 1024Mbits(64Mbx16) 12
Page
16X16
USB conn x2 daughter board
Page 31
LVDS Panel ATI RS880M
Interface Page 17 DDR2 400MHz BT Conn Page 31 New Module
CRT
Page 16 Page 10, 11, 12, 13, 14
2 Mini-Card WWAN
Page 26
2
USB2.0 X12
HDMI A-Link Express II
Page 18
4X PCI-E
USB conn x1
Page 31
PCI-E BUS*5 Azalia (HDA I/F)
USB WebCam
SATA Master-1 Module
ATI SB710 SATA Master-2
Page 17
SATA Slave
CardReader Realtek Mini-Card*2 Express Card FingerPrinter AES1610
JMicron 8102E(10/100M) WLAN & WWAN
SATA Slave Module
Page 26 Page 19, 20, 21, 22, 23 USBx1 page 35
JMB385-LGEZ0A
Page 27 Page 25 Page 26
MDC V1.5 daughter board
Page 34
RJ45/11 CONN LPC BUS Audio CKT
3
CardReader Socket Page 25 AMP & Audio Jack
3
Codec_IDT9271B7
Page 27 Page 28 TPA6017A2 Page 29
KBC SATA HDD Connector
ENE KB926-C0 Page 24
Page 33
Docking CONN. LED SATA ODD Connector
Page 24
*RJ-45(LED*2) P41 Touch Pad CONN.
Page 34
Int.KBD
Page 33
*RJ-11(Pass Through) Multi-Bay HDD/ODD Option Connector
*CRT Page 24
*COMPOSITE Video Out
RTC CKT.
*S-VIDEO OUT Page 19
Consumer IR SPI SPI ROM e-SATA Connector
*SPDIF MX25L1605
Page 34 Page 31
*Headphone/Line Out L/R Power OK CKT. AM2C-12G
Page 32
*Stereo Mic L/R P35
4
*Volume Control 4
*Consumer IR
*USB x1 Power On/Off CKT.
*DC JACK P35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
DC/DC Interface CKT. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Page 35 Page 36 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 2 of 56
A B C D E
A B C D E
Symbol Note : 1.0/1.0a
For Riply PA-> PA@, RP@
: means Digital Ground For Riply PR-> PR@, RP@, PRM@
For Rachman UMA-> RM@, PRM@
O MEANS ON X MEANS OFF
Voltage Rails RP10@
Z ZZ
RM10@
Z ZZ
: means Analog Ground
1 PCB for 1.0/1.0a 1
L Layout Notes
PCB-Ripley MB PCB-Rachman UMA MB
+5VS Please see VGA@ as no install. No support RX780M. DAZ=DAZ03Y00201 DAZ=DAZ03Y00101
+3VS
+1.5VS : Question Area Mark.(Wait check) RP11@,RM11@:For 1.A PCB
power
plane +0.9V RP10@,RM10@:For 1.0 PCB.
+VCCP "*" as default BOM setting
+5VALW +1.8V +CPU_CORE *PA@ : means install when Ripley PA. U3 U15
+B PR@ : means install when Ripley PR.
SB700
+3VALW +VGA_CORE RM@ : means install when Rachman. RS780
+2.5VS *RP@ : means install when Ripley. RS780 R1 SB700 R1
RS780R1@ SBR1@
State +1.8VS SIDE@ : means install when SidePort support.
+1.2VS @ : means just reserve , no build
+0.9VGA 45@ : Install when 45 level Assy
2 R3 NB and SB: RS780R3@,SBR3@ 2
R1 NB and SB: RS780R1@,SBR1@
S0
O O O O
RP11@ RM11@
1.1 Z ZZ Z ZZ
S1
O O O O For Riply PA-> PA@, RP@,RPZ@ PCB for 1.1
S3 For Riply PR-> PR@, RP@, PRM@,RPZ@
O O O X For Rachman UMA-> RM@, PRM@,RMZ@ PCB-Ripley MB PCB-Rachman UMA MB
DAZ=DAZ03Y00203 DAZ=DAZ03Y00102
S5 S4/AC 2.0
O O X X RP@ RM@ X76
Z ZZ Z ZZ
S5 S4/ Battery only For Riply PA-> PA@/RP@/RPZ@
O X X X PCB for 2.0
X76
S5 S4/AC & Battery For Rachman UMA-> RM@/PRM@/RMZ@ PCB-Ripley MB PCB-Rachman UMA MB
don't exist X X X X SMBUS Control Table
DAZ=DAZ09000102 DAZ=DAZ09100102
THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM CPU & SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor
ADM1032 I / II Slot 2
3 3
SMB_EC_CK1
I2C / SMBUS ADDRESSING KB926 X V V VCPU X X X X X X
SMB_EC_DA1
SMB_EC_CK2
DEVICE HEX ADDRESS SMB_EC_DA2
KB926 X X X V
ADM1032 X X X X X X
DDR SO-DIMM 0 A0 10100000 I2C_CLK
DDR SO-DIMM 1 A4 10100100 I2C_DATA
RS780M
X X X X X X X V X X
CL OCK GENERATOR (EXT.) D2 11010010 DDC_CLK0
DDC_DATA0
RS780M X X X X X X X X V X
DDC_CLK1
EC SM Bus1 address EC SM Bus2 address DDC_DATA1
RS780M X X X X X X X X X X
SCL0
Device HEX Address Device HEX Address
SDA0
SB700 X X X X V V X X X X
Smart Battery 16H 0001 011X b CPU 98H 1001 100X b SCL1
24C16 A0H 1010 000X b ADI1032-2 CPU 9AH 1001 101X b SDA1
SB700 X X X X X X V X X X
SCL2
SDA2
SB700 X X X X X X X X X V
4 4
SCL3
SDA3
SB700 X X X X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 3 of 56
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
<10> H_CADIN[0..15] H_CADON[0..15] <10>
Near CPU Socket
+1.2V_HT
JCPUA
VLDT=500mA D1 HT LINK AE2 +VLDT_B 1 2
VLDT_A0 VLDT_B0 C7 4.7U_0805_10V4Z
D2 VLDT_A1 VLDT_B1 AE3
D3 AE4 If VLDT is connected only on one side, one
VLDT_A2 VLDT_B2 4.7uF cap should be added to the island
D4 AE5
VLDT_A3 VLDT_B3 side.
H_CADIP0 E3 AD1 H_CADOP0
H _CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 AC1
H_CADIP1 L0_CADIN_L0 L0_CADOUT_L0 H_CADOP1
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
H _CADIN1 F1 AC3 H_CADON1
H_CADIP2 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP2
G3 AB1
H _CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 AA1
2 H_CADIP3 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP3 2
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H _CADIN3 H1 AA3 H_CADON3
H_CADIP4 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP4
J1 W2
H _CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H _CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 U1
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H _CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H _CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H _CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
H _CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 AB4
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 AB3
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 AB5
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 V3
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 V5
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 T4
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15 +5VS
P5 T3
L0_CADIN_L15 L0_CADOUT_L15
J3 Y1
<10>
<10>
H_CLKIP0
H_CLKIN0 J2
J5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKOUT_H0
L0_CLKOUT_L0
W1
Y4
H_CLKOP0
H_CLKON0
<10>
<10> PWM Fan Control circuit JP2
<10> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <10>
1
<10> H_CLKIN1 K5 Y3 H_CLKON1 <10> 1 1 1
L0_CLKIN_L1 L0_CLKOUT_L1 C8 C9 1
2
3 D1 0.1U_0402_16V4Z 2 3
<10> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <10>
P1 R3 CH751H-40PT_SOD323-2 4.7U_0805_10V4Z 3
<10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10> 2 2 GND
<10> H_CTLIP1 P3 T5 H_CTLOP1 <10> 4
2
L0_CTLIN_H1 L0_CTLOUT_H1 GND
<10> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <10>
ACES_88231-02001
+VCC_FAN CONN@
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
1
2
5
6
1
Athlon 64 S1
Processor Socket D Q1 @ D2
9/20 SP07000DM00/SP07000EQ00 G
3 RLZ5.1B_LL34
<33> FAN_PWM S SI3456BDV-T1-E3_TSOP6
2
4
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 4 of 56
A B C D E
A B C D E
Processor DDR2 Memory Interface
PLACE CLOSE TO PROCESSOR
1 WITHIN 1.5 INCH 1
JCPUC
<9> DDR_B_D[63..0]
MEM:DATA
DDR_A_CLK0 DDR_B_D0 DDR_A_D0 DDR_A_D[63..0] <8>
C11 MB_DATA0 MA_DATA0 G12
1 DDR_B_D1 A11 F12 DDR_A_D1
DDR_B_D2 MB_DATA1 MA_DATA1 DDR_A_D2
A14 H14
C10 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3
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