Service Manuals, User Guides, Schematic Diagrams or docs for : DENON Audio DN-X1500 Denon DN-X1500 - VER.1
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For U.S.A., Canada, Europe,
Oceania & Asia model
Ver. 1
SERVICE MANUAL
MODEL DN-X1500
DJ MIXER
For purposes of improvement, specifications and
design are subject to change without notice.
Please use this service manual with referring to ,
the operating instructions without fail.
Some illustrations using in this service manual are
slightly different from the actual set.
16-11, YUSHIMA 3-CHOME, BUNKYO-KU, TOKYO 113-0034 JAPAN
X-0196V.01 DE/CDM 0401
DN-X1500 2
SAFETY PRECAUTIONS
LEAKAGE CURRENT CHECK
LASER RADIATION
500V
1M
(1)
(2)
(1)
(2)
2
DN-X1500 3
DISASSEMBLY
(Follow the procedure below in reverse order when reassembling.)
1. Top Panel Unit
(1)Remove 9 screws and pull up Top Panel Unit.
(2)Disconnect FFC cable and Connector.
(3)Detach Top Panel Unit.
Note: Do not pull out aslsnt to prevent FFC cable damage.
Do not fail to pull AC cord from wall outlet before
disconnect the FFC cable.
if AC cord is remained plugged into wall outlet,
power is kept supplied in the unit, which may cause
danger.
Top Panel Unit
2. Cross Feder Unit
(1)Remove 2 screws and pull up Cross Feder Unit.
(2)Disconnect Connector.
Cross Feder Unit
Connector
Label face
3
DN-X1500 4
3. CH Fader Unit
(1)Remove 4 knobs.
(2)Remove 4 screws and pull up CH Fader Panel.
(3)Remove 2 screws for each CH.
(4)Disconnect Connector.
(5)Detach CH Fader Unit.
4. Front Panel
(1)Pull out the knobs.
(2)Remove 8 screws.
(3)Pull up Front Panel.
Front Panel
4
DN-X1500 5
SERVICE MODE SPECIFICATION
*How the product performs when the operation buttons for com control are pressed (including control input) is described in
the table below.
1. POWER ON
Function Description Display Remarks
POWER (1)Turns power ON/OFF.
(2)Switches power ON when OFF. Displays Service . Refer to CH GAIN VR.
Enters in the service mode when power on Refer to MASTER LEVEL VR.
Service
while pressing MIC POST ON/OFF button and Refer to SAMPER ASSIGN.
Mode
EFFECT LOOP ON/OFF but ton. Refer to CROSSFADER ASSIGN.
For canceling the service mode, turn power off/on.
2. CH GAIN VR
Function Description Display Remarks
CH LEVEL (1) When you turn this VR, LED of CH level meter VR position is 0 : LED is not lit.
METER is lit. VR position is 10 : All LED is lit.
3. MASTER LEVEL VR
Function Description Display Remarks
MASTER (1) When you turn this VR, LED of master level VR position is 0 : LED is not lit.
LEVEL meter is lit. VR position is 10 : All LED is lit.
METER
4. (SAMPLER) CROSSFADER ASSIGN switch
Function Description Display Remarks
(1) You can select FL display mode. A : FL tube is not lit.
B : All FL tube is lit.
FL mode
POST : Displays VR checking or
LED checking.
5
DN-X1500 6
5. SAMPLER ASSIGN switch
Function Description Display Remarks
FADER VR (1)When CROSSFADER ASSIGN switch is set Refer to CROSSFAER ASSGIN.
CHECK to POST, you can check the fader VR and LED.
(1)When selected OFF, it becomes the LED off Displays LED OFF .
OFF
modde.
(1)When selected CH1, it becomes the mode of Displays 0 100 .
CH1 reading/displaying CH1 fader VR value. Fader position is 0 : 0
Fader position is 10 : 100
(1)When selected CH2, it becomes the mode of Displays 0 100 .
CH2 reading/displaying CH2 fader VR value. Fader position is 0 : 0
Fader position is 10 : 100
(1)When selected CH3, it becomes the mode of Displays 0 100 .
CH3 reading/displaying CH3 fader VR value. Fader position is 0 : 0
Fader position is 10 : 100
(1)When selected CH4, it becomes the mode of Displays 0 100 .
CH4 reading/displaying CH4 fader VR value. Fader position is 0 : 0
Fader position is 10 : 100
MAIN (1)When selected MAIN MIC, it becomes the Displays LED ON .
MIC LED on mode.
(1)When selected MASTER, it becomes the Displays 0 100 .
MASTER mode of reading/displaying crossfader VR value. Fader position is Left side : 0
Fader position is Right side : 100
6. COM VERSION CHECK
You can check the com version at Preset Functions .
Please refer to the Instructions Manual.
6
DN-X1500 7
SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
IC's
Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc.
MN102H74D (IC101)
75 51
76 50
100 26
1 25
MN102H74D Terminal Function
Int
No. Pin Name Symbol I/O DET PU Ext Res Ini Function
1 P50,WAIT _WAIT I - - Pu H - HI R/W timing wait signal
2 P51,_RE _RD O - - Pu H - Read signal
3 P52,_WEL _WEL O - - Pu H - Write signal
4 P53,_WEH _DSP_REQ O - ON - Hi-z H System <-> DSP REQ signal
5 P60,_CS0 _CS0 O - - Pu H - Chip select signal 1st address of Flash ROM:
6 P61,_CS1 _CS_DSP O - - Pu H - Chip select of expansion port
7 P62,_CS2 _HBR O - - Pu H - DSP select signal Host Interface
8 P63,_CS3 _DSP_ACK I - ON - Hi-z - System <-> DSP ACK signal
Panel ucom control: When DSP boot, system bus
9 P64,TM0IO,_BREQ _BREQ I - - Pu H - open. 'L': open
10 P65,TM1IO,_BRACK _BRACK O - Pu H - When bus open, 'L' output.
11 P66,_WR _DAC_RST O - ON - H H Reset of ADC, DAC, and DIT
12 _WORD _WORD I - - L L - Select width of data bit bus 'L': 16bit
13 P20,A00 A00 A/O - ON - Hi-z - Address bus
14 P21,A01 A01 A/O - ON - Hi-z - Address bus
15 P22,A02 A02 A/O - ON - Hi-z - Address bus
16 P23,A03 A03 A/O - ON - Hi-z - Address bus
17 Vdd Vdd - - - - - - Power supply(+3.3V)
18 P54,BOSC,SYSCLK RESERVE1 O - ON - L H Signal for test
19 Vss Vss - - - - - - GND(0V)
20 XI XI - - - - - - Not used
21 XO XO - - - - - - Not used
22 Vdd Vdd - - - - - - Power supply(+3.3V)
23 OSCI OSCI I - - - - - This Need 12MHz for USB communication
24 OSCO OSCO O - - - - - Output OSCI
Mode set
25 MODE MODE I - - H H - 'H': Memory expansion/single chip mode
26 P24,A04 A04 A/O - ON - Hi-z - Address bus
27 P25,A05 A05 A/O - ON - Hi-z - Address bus
28 P26,A06 A06 A/O - ON - Hi-z - Address bus
29 P27,A07 A07 A/O - ON - Hi-z - Address bus
30 P30,A08 A08 A/O - ON - Hi-z - Address bus
31 P31,A09 A09 A/O - ON - Hi-z - Address bus
32 P32,A10 A10 A/O - ON - Hi-z - Address bus
33 P33,A11 A11 A/O - ON - Hi-z - Address bus
34 Vdd Vdd - - - - - - Power supply(+3.3V)
35 P34,A12 A12 A/O - ON - Hi-z - Address bus
36 P35,A13 A13 A/O - ON - Hi-z - Address bus
37 P36,A14 A14 A/O - ON - Hi-z - Address bus
38 P37,A15 A15 A/O - ON - Hi-z - Address bus
Internal Pull Up is 10 90 ( K ), Ave : 30 ( K )
7
DN-X1500 8
Int
No. Pin Name Symbol I/O DET PU Ext Res Ini Function
39 P40,A16 A16 A/O - ON - Hi-z -Address bus
40 P41,A17 A17 A/O - ON - Hi-z -Address bus
41 P42,A18 A18 A/O - ON - Hi-z -Address bus
Address bus
42 P43,(TM2IO),A19 A19 A/O - - Pu H - Need pull up to extension for DSP boot control
43 Vss Vss - - - - - - GND(0V)
44 P44,(TM3IO),A20 _CDDEC_LC O - ON - Hi-z H Latch to codec1 'L': available
45 P45,(TM4IO),A21 _CDDEC_LC O - ON - Hi-z H Latch to codec2 'L': available
46 P46,(TM5IO),A22 _DAC_CS O - ON - Hi-z H DAC chip select 'L': available
DIT chip select
47 P47,_CS0S,(TM6IO),A23 _DIT_CS O - - Pd L H 'L': available (be pull down in DSP)
48 P70,_CS1S,(TM7IO),SBI3 DIT_DIN I - ON - Hi-z H DIT data input
CODEC(AD1838A)/DAC(PCM1791A)/DIT(AK4103)
49 P71,_CS2S,(TM8IO),SBO3 CLOCK_A O - - Pd L L data output clock signal
CODEC(AD1838A)/DAC(PCM1791A)/DIT(AK4103)
50 P72,_CS3S,(TM9IO),SBT3 DATA_A O - ON - Hi-z L data signal
Lch SEND/RETURN connection status
51 P80,TM10IOA,WDOUT PLGIN_L I - - Pu H H 'H': connect
Rch SEND/RETURN connection status
52 P81,TM10IOB,STOP PLGIN_R I - - Pu H H 'H': connect
53 USBMODE USBMODE - - - - - - USB mode selectable terminal, connect to GND
54 Vdd Vdd - - - - - - Power supply(+3.3V)
Connect USB terminal D+. 24 resistance is
55 D+ D+ - - - Pu - - connected in series.
Connect USB terminal D-. 24 resistance is
56 D- D- - - - - - - connected in series.
57 Vss Vss - - - - - - GND(0V)
58 P82,SBI2 RxD I - - Pu H - 75000bps Need to convert level
59 P83,SBO2,TM11IOA TxD O - - Pu H H 75000bps Need to convert level
60 P84,SBT2,TM11IOB _MONO I - ON - Hi-z - MONO/STEREO SW 'L': MONO
61 Vss Vss - - - - - - GND(0V)
62 P90,AN0,TM12IOA ATT I Ad - - - - Adjust VR for Master output (BAL/UNBAL)
TC94A32/TC9162 ALL STB set to L
63 P91,AN1,TM12IOB _STB_CLR O - - Pd L L 'L': L set , CODEC reset
Electric VR(TC94A32)/SelectorTC9162 data output
64 P92,AN2,TM13IOA CLOCK_B O - - Pd L L clock signal
65 P93,AN3,TM13IOB DATA_B O - ON - Hi-z L Electric VR(TC94A32)/SelectorTC9162 data signal
66 Vdd Vdd - - - - - - Power supply(+3.3V)
67 PA0,SBI1,AN4 _FPLAY1 O - - Pu H H Ch1 Fader PLAY output 20msec 'L' pulse
68 PA1,SBO1,AN5,SDA1 _FCUE1 O - - Pu H H Ch1 Fader CUE output 20msec 'L' pulse
69 PA2,SBT1,AN6,SCL1 _FPLAY2 O - - Pu H H Ch2 Fader PLAY output 20msec 'L' pulse
70 PA3,SBI0,AN7 _FCUE2 O - - Pu H H Ch2 Fader CUE output 20msec 'L' pulse
71 PA4,SBO0,SDA0 _FPLAY3 O - - Pu H H Ch3 Fader PLAY output 20msec 'L' pulse
72 PA5,SBT0,SCL0 _FCUE3 O - - Pu H H Ch3 Fader CUE output 20msec 'L' pulse
Pull up 4.7k 10k Connection output for
73 TEST1 SBD4 I - - Pu - - onboard write of internal form.
Pull up 4.7k 10k Connection output for
74 TEST2 SBT4 I - - Pu - - onboard write of internal form.
75 _NMI _NMI I Lv - - H H
76 PB0,_IRQ0 _DSP_BPM I Ed ON - - Trigger terminal for BPM counter by DSP
77 PB1,_IRQ1 DSP_COM O - - Pu H - System <-> DSP REQ2 signal
78 PB2,_IRQ2 RESERVE4 I - - Pu H - Signal for test
79 PB3,_IRQ3 MUTE O - - Pu H H Analog/Digital mute 'H': Mute ON
80 PB4,_IRQ4 _FPLAY4 O - - Pu H H Ch4 Fader PLAY output 20msec 'L' pulse
81 PB5,_IRQ5 _FCUE4 O - - Pu H H Ch4 Fader CUE output 20msec 'L' pulse
82 _RST _RESET I Lv - - L - Reset signal 'L': Reset
83 Vdd Vdd - - - - - - Power supply(+3.3V)
84 P00,D00 D00 D/O - ON - Hi-Z - Data bus
85 P01,D01 D01 D/O - ON - Hi-Z - Data bus
86 P02,D02 D02 D/O - ON - Hi-Z - Data bus
87 P03,D03 D03 D/O - ON - Hi-Z - Data bus
88 P04,D04 D04 D/O - ON - Hi-Z - Data bus
89 P05,D05 D05 D/O - ON - Hi-Z - Data bus
90 P06,D06 D06 D/O - ON - Hi-Z - Data bus
91 P07,D07 D07 D/O - ON - Hi-Z - Data bus
92 Vss Vss - - - - - - GND(0V)
93 P010,D08,(TM2IO) D08 D/O - ON - Hi-Z - Data bus
94 P011,D09,(TM3IO) D09 D/O - ON - Hi-Z - Data bus
95 P012,D10,(TM4IO) D10 D/O - ON - Hi-Z - Data bus
96 P013,D11,(TM5IO) D11 D/O - ON - Hi-Z - Data bus
97 P014,D12,(TM6IO) D12 D/O - ON - Hi-Z - Data bus
98 P015,D13,(TM7IO) D13 D/O - ON - Hi-Z - Data bus
99 P016,D14,(TM8IO) D14 D/O - ON - Hi-Z - Data bus
100 P017,D15,(TM9IO) D15 D/O - ON - Hi-Z - Data bus
8
DN-X1500 9
TMP86CM47U (IC301)
33 23
34 22
TOP VIEW
44 12
1 11
TMP86CM47U Terminal Function
Pin No. Pin Name Symbol I/O DET Ext Res Ini Function
1 VSS VSS - - - - - GND (0V)
2 XIN XIN - - - - - Oscillation input 16MHz
3 XOUT XOUT - - - - - Oscillation output
4 TEST TEST - - - - - Fixed to GND
5 VDD VDD - - - - - Power (+5.0V)
6 P21 ADR1 O - Pu - H Address decode signal 1
7 P22 ADR2 O - Pu - H Address decode signal 2
8 RESET_ RESET_ - - - - - Reset input
9 P20 DSPBSY I - Pu H - Boot flag (L: during boot)
10 P00 ADR3 O - Pu - H Address decode signal 3
11 P01 ADR4 O - Pu - H Address decode signal 4
12 RXD RXD I - - H - Serial receive signal
13 TXD TXD O - Pu H H Serial send signal
14 SO FLSD O - Pu H H M66005AFP-SDATA
15 P05 FLCS O - Pu H H M66005AFP-CA
16 SCK FLCLK O - Pu H H M66005AFP-CLK
17 P07 TEST1 O - - - H Not used
18 P17 FLRST O - Pd L L M66005AFP reset signal (L: Reset)
19 P16 DRST O - Pd L L DSP reset (L: Reset)
20 P15 BREQ O - Pu H H System ucom stop signal
21 P14 LDLCH O - Pu H H LED driver latch signal
22 P13 LDCLK O - Pu - H Clock for LED driver data sending
23 P12 LDDAT1 O - Pd - L LED driver data 1
24 P11 LDDAT2 O - Pd - L LED driver data 2
25 P10 LDDAT3 O - L L L LED driver data 3
26 AIN0 KEYIN0 I - - - - Key input 0 (Volume)
27 AIN1 KEYIN1 I - - - - Key input 1 (Volume)
28 AIN2 KEYIN2 I - - - - Key input 2 (Volume)
29 AIN3 KEYIN3 I - - - - Key input 3 (Volume)
30 AIN4 KEYIN4 I - - - - Key input 4 (Volume)
31 AIN5 KEYIN5 I - - - - Key input 5 (Volume)
32 AIN6 KEYIN6 I - - - - Key input 6 (Volume)
33 AIN7 KEYIN7 I - - - - Key input 7 (Volume)
34 VAREF VARFF - - - - - Power (+5.0V), Analog ref.V for A/D conversion
35 AVDD AVDD - - - - - Power (+5.0V)
36 AVSS AVSS - - - - - GND (0V), Analog GND for A/D conversion
37 P40 KEYIN8 I - Pu - H Key input 8 (Key matrix)
38 P41 KEYIN9 I - Pu - H Key input 9 (Key matrix)
39 P42 KEYIN10 I - Pu - H Key input 10 (Key matrix)
40 P43 KEYIN11 I - Pu - H Key input 11 (Key matrix)
41 P44 KEYIN12 I - Pu - H Key input 12 (Key matrix)
42 P45 KEYIN13 I - Pu - H Key input 13 (Key matrix)
43 P46 KEYIN14 I - Pu - H Key input 14 (Key matrix)
44 P47 KEYIN15 I - Pu - H Key input 15 (Key matrix)
9
DN-X1500 10
ADSST-MEL100 (DSP:IC101)
14 12 10 8 6 4 2
15 13 11 9 7 5 3 1
A
B
C
D
E
F
G
TOP VIEW H
J
K
L
M
N
P
R
BOTTOM VIEW
ADSST-MEL100 Terminal Function
No. Pin Name No. Pin Name No. Pin Name No. Pin Name No. Pin Name
A 1 NC B 1 TRST_ C 1 TMS D 1 TD0 E 1 FLAG10
A 2 BMSTR B 2 TDI C 2 EMU_ D 2 TCK E 2 RESET_
A 3 BMS_ B 3 RPBA C 3 GND D 3 FLAG11 E 3 FLAG8
A 4 SPIDS_ B 4 MOSI C 4 SPICLK D 4 MISO E 4 D0A
A 5 EBOOT B 5 FS0 C 5 D0B D 5 SCLK0 E 5 VDDEXT
A 6 LBOOT B 6 SCLK1 C 6 D1A D 6 D1B E 6 VDDINT
A 7 SCLK2 B 7 D2B C 7 D2A D 7 FS1 E 7 VDDEXT
A 8 D3B B 8 D3A C 8 FS2 D 8 VDDINT E 8 VDDINT
A 9 L0DAT[4] B 9 L0DAT[7] C 9 FS3 D 9 SCLK3 E 9 VDDEXT
A 10 L0ACK B 10 L0CLK C 10 L0DAT[6] D 10 L0DAT[5] E 10 VDDINT
A 11 L0DAT[2] B 11 L0DAT[1] C 11 L1DAT[7] D 11 L0DAT[3] E 11 VDDEXT
A 12 L1DAT[6] B 12 L1DAT[4] C 12 L1DAT[3] D 12 L1DAT[5] E 12 L0DAT[0]
A 13 L1CLK B 13 L1ACK C 13 L1DAT[1] D 13 DATA[42] E 13 DATA[39]
A 14 L1DAT[2] B 14 L1DAT[0] C 14 DATA[45] D 14 DATA[46] E 14 DATA[43]
A 15 NC B 15 RSTOUT_ C 15 DATA[47] D 15 DATA[44] E 15 DATA[41]
No. Pin Name No. Pin Name No. Pin Name No. Pin Name No. Pin Name
F 1 FLAG5 G 1 FLAG1 H 1 FLAG0 J 1 IRQ2_ K 1 TIMEXP
F 2 FLAG7 G 2 FLAG2 H 2 IRQ0_ J 2 ID1 K 2 ADDR[22]
F 3 FLAG9 G 3 FLAG4 H 3 VDDINT J 3 ID2 K 3 ADDR[20]
F 4 FLAG6 G 4 FLAG3 H 4 IRQ1_ J 4 ID0 K 4 ADDR[23]
F 5 VDDINT G 5 VDDEXT H 5 VDDINT J 5 VDDEXT K 5 VDDINT
F 6 GND G 6 GND H 6 GND J 6 GND K 6 GND
F 7 GND G 7 GND H 7 GND J 7 GND K 7 GND
F 8 GND G 8 GND H 8 GND J 8 GND K 8 GND
F 9 GND G 9 GND H 9 GND J 9 GND K 9 GND
F 10 GND G 10 GND H 10 GND J 10 GND K 10 GND
F 11 VDDINT G 11 VDDEXT H 11 VDDINT J 11 VDDEXT K 11 VDDINT
F 12 DATA[37] G 12 DATA[34] H 12 DATA[29] J 12 DATA[26] K 12 DATA[22]
F 13 DATA[40] G 13 DATA[35] H 13 DATA[28] J 13 DATA[24] K 13 DATA[19]
F 14 DATA[38] G 14 DATA[33] H 14 DATA[30] J 14 DATA[25] K 14 DATA[21]
F 15 DATA[36] G 15 DATA[32] H 15 DATA[31] J 15 DATA[27] K 15 DATA[23]
No. Pin Name No. Pin Name No. Pin Name No. Pin Name No. Pin Name
L 1 ADDR[19] M 1 ADDR[16] N 1 ADDR[14] P 1 ADDR[13] R 1 NC
L 2 ADDR[17] M 2 ADDR[12] N 2 ADDR[15] P 2 ADDR[9] R 2 ADDR[11]
L 3 ADDR[21] M 3 ADDR[18] N 3 ADDR[10] P 3 ADDR[8] R 3 ADDR[7]
L 4 ADDR[2] M 4 ADDR[6] N 4 ADDR[5] P 4 ADDR[4] R 4 ADDR[3]
L 5 VDDEXT M 5 ADDR[0] N 5 ADDR[1] P 5 MS2 R 5 MS3
L 6 VDDINT M 6 MS1 N 6 MS0 P 6 SBTS_ R 6 PA
L 7 VDDEXT M 7 BR6 N 7 BR5 P 7 BR4 R 7 BR3
L 8 VDDINT M 8 VDDEXT N 8 BR2 P 8 BR1 R 8 RD
L 9 VDDEXT M 9 WR N 9 BRST P 9 SDCLK1 R 9 CLKOUT
L 10 VDDINT M 10 SDA10 N 10 SDCKE P 10 SDCLK0 R 10 HBR
L 11 VDDEXT M 11 RAS_ N 11 CS_ P 11 REDY R 11 HBG
L 12 CAS_ M 12 ACK N 12 CLK_CFG1 P 12 CLKIN R 12 CLKDBL
L 13 DATA[20] M 13 DATA[17] N 13 CLK_CFG0 P 13 DQM R 13 XTAL
L 14 DATA[16] M 14 DMAG2 N 14 AVDD P 14 AVSS R 14 SDWE_
L 15 DATA[18] M 15 DMAG1 N 15 DMAR1 P 15 DMAR2 R 15 NC
10
DN-X1500 11
128M-SDRAM (DSP:IC102)
VDD 1 86 VSS
DQ0 2 85 DQ15
VDDQ 3 84 VSSQ
DQ1 4 83 DQ14
DQ2 5 82 DQ13
VSSQ 6 81 VDDQ
DQ3 7 80 DQ12
DQ4 8 79 DQ11
VDDQ 9 78 VSSQ
DQ5 10 77 DQ10
DQ6 11 76 DQ9
VSSQ 12 75 VDDQ
DQ7 13 74 DQ8
NC 14 73 NC
VDD 15 72 VSS
DQM0 16 71 DQM1
WE# 17 70 NC
CAS# 18 69 NC
RAS# 19 68 CLK
CS# 20 67 CKE
A11 21 66 A9
BA0 22 65 A8
BA1 23 64 A7
A10 24 63 A6
A0 25 62 A5
A1 26 61 A4
A2 27 60 A3
DQM2 28 59 DQM3
VDD 29 58 VSS
NC 30 57 NC
DQ16 31 56 DQ31
VSSQ 32 55 VDDQ
DQ17 33 54 DQ30
DQ18 34 53 DQ29
VDDQ 35 52 VSSQ
DQ19 36 51 DQ28
DQ20 37 50 DQ27
VSSQ 38 49 VDDQ
DQ21 39 48 DQ26
DQ22 40 47 DQ25
VDDQ 41 46 VSSQ
DQ23 42 45 DQ24
VDD 43 44 VSS
Note: The # symbol indicates signal is active LOW.
Block Diagram
CKE
CLK
CS# CONTROL
COMMAND
LOGIC
DECODE
WE#
BANK3
CAS# BANK2
RAS# BANK1
BANK0
REFRESH 12
MODE REGISTER COUNTER
ROW- 12 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 4 4
12 4096
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