Service Manuals, User Guides, Schematic Diagrams or docs for : Dell Dell_m1330_Thurman_Discrete_VGA_nVidia_G86
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5 4 3 2 1
D D
Thurman Discrete VGA nVidia G86 Schematics Document
C
uFCPGA Mobile Merom C
Intel Crestline-PM + ICH8M
2007-11-06
B B
REV : -1(DELL:A00)
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Thurman Discrete
Size Document Number Rev
A3 COVER PAGE -1
Date: Tuesday, November 06, 2007 Sheet 1 of 50
5 4 3 2 1
5 4 3 2 1
System DC/DC
Thurman Discrete Block Diagram TPS51120
INPUTS OUTPUTS
45
Project code:91.4C301.001 +PWR_SRC
+5V_ALW +5V_SUS
+3.3V_SUS
+3.3V_RTC_LDO
PCB P/N :06247 System DC/DC
Thermal Sensor Clock Generator Intel Mobile CPU
D EMC4001 28 CY28547LFXC 6 Merom 4M
REVISION :-1 TPS51124 46
D
SMBus +PWR_SRC +1.05V_VCCP
FSB:667/ 800 Mhz +1.5V_RUN
7,8 DDR2 DC/DC
VRAM VRAM 200-PIN DDR2 SODIMM TPS51117 47
16MX32 21 16MX32 21 HOST BUS FSB 667/800MHz
RGB UNBUFFERED +1.8V_SUS
CRT DDRII 533/667MHz LDO 48 +PWR_SRC
22 DDRIII 700MHz DDRIII 700MHz DDR2 SODIMM SC339SKTRT
Crestline-PM Socket
15 +PWR_SRC +1.25V_RUN LDO
LCD
LVDS 47
23 PCI-e x16 TPS51100
nVidia nB8M
17,18,19 AGTL+ CPU I/F UNBUFFERED +1.8V_SUS +0.9V_DDR_VTT
HDMI DDRII 533/667MHz V_DDR_MCH_REF
HDMI
22
DDR Memory I/F DDR2 SODIMM 1394
1394 VGA DC/DC
EXTERNAL GRAHPICS Socket Ricoh R5C833 CONN 33
16 TPS51117 48
8 in 1 card reader
7 in1 8 in1
SPDIF 9,10,11,12,13,14 1394 +PWR_SRC VGA_CORE
C
32 CONN 33 C
Power Switch
DMI x4 C-LINK0 PCI BUS 30 Express Card
PCI Express (4) PCIE#4 Slot 54mm
SATA Intel USB#6 30 Battery Charger
SATA HDD 30 ICH8-M USB#7 MAX8731 42
PATA IDE
Enhanced Buletooth 2.1 33 INPUTS OUTPUTS
ODD Bay USB 2.0/1.1 ports (10) USB2.0 (7)
30 USB#0
PCI Express ports (6) USB*1 left side42 +PWR_SRC +VCHGR
High Definition Audio USB#1 USB*1 Right side CPU DC/DC
42 ISL6260C 43,44
ATA 66/ 100
Headphone AMP. SATA (3) Mini-Card SIM INPUTS OUTPUTS
PCIE#1
LINE OUT / HP MAX4401A LPC I/F WWAN 31 CONN 31 +PWR_SRC +VCC_CORE
35 SPI
B
ACPI 1.1
USB#9 B
Mini-Card
PCIE#2
PCI/PCI BRIDGE 802.11a/g/n 31 PCB LAYER
Digital MIC23 Azalia CODEC AZALIA 24,25,26,27 PCIE#6 RJ45
STAC 9228 LAN BCM5906 L1:TOP
MIC IN 34 CONN 29
10/100 NIC 29
SPI
LPC
L2:GND
BIOS
USB#5 L3:Signal
LINE OUT / HP SPI FLASH SPI Camera 23
Headphone AMP. 16Mb 37
MAX9789A EC SIO Expander L4:Signal
35 BC
INT. SPKR *2 SMSC MEC5025 SMSC ECE5021 L5:VCC
35 36 37
L6:Signal
BC
PS/2 L7:GND
CIR
LCD 42 USB#4
A 23 L8:BOT A
Digital MIC LCD Module KBC Wistron Corporation
23 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Int. KB Touch Taipei Hsien 221, Taiwan, R.O.C.
SMSC ECE1077 Biometric
38 38
Pad 38 38 Title
Camera 23
38 Thurman Discrete
Touch Pad Module Size Document Number Rev
A3 BLOCK DIAGRAM -1
Date: Tuesday, November 06, 2007 Sheet 2 of 50
5 4 3 2 1
5 4 3 2 1
ICH8 SMBus Block Diagram KBC SMBus Block Diagram +3.3V_ALW +3.3V_RUN
+3.3V_SUS +3.3V_RUN
+3.3V_RUN
SRN2K2J-1-GP SRN2K2J-1-GP
+3.3V_RUN
SRN2K2J-1-GP
SRN4K7J-8-GP
KSO17/GPIOA1/AB1H_DATA CKG_SMBDAT
CLK GEN.
CLK_SDATA SDATA
D
ICH8-M DIMM 1 KSO16/GPIOA0/AB1H_CLK CKG_SMBCLK
CLK_SCLK SCLK
D
SMBCLK ICH_SMBCLK
MEM_SCLK
SCL
(Reverse Type)
SMBDATA ICH_SMBDATA
MEM_SDATA
SDA
+5V_ALW 2N7002DW-7F-GP
+5V_RUN SMBus address:D2
SMBus Address : A0
2N7002DW-7F-GP
MEM_SCLK
DIMM 2 SRN2K2J-1-GP
+5V_RUN
SCL SRN2K2J-1-GP
MEM_SDATA
(Reverse Type)
SDA
Capacity Button
SMBus Address : A4 AB1A_DATA DOCK_SMBDAT
DOCK_SMBDAT_C SDATA
AB1A_CLK
DOCK_SMBCLK
DOCK_SMBCLK_C SCLK Board
Express SMBus address:86
WWAN
Card 2N7002DW-7F-GP
ICH_SMBCLK
SMB_CLK
MEM_SCLK
Minicard +3.3V_ALW
ICH_SMBDATA SMB_CLK
SMB_DATA MEM_SDATA
SMB_DATA
SIO
C
MEC5025 SRN2K2J-1-GP C
+3.3V_WLAN
Battery Conn.
GPIO87/AB1C_DATA PBAT_SMBDAT
100R2F-L1-GP-U PBAT_SMBCLK1 CLK_SMB
+3.3V_SUS
GPIO86/AB1C_CLK PBAT_SMBCLK
100R2F-L1-GP-U PBAT_SMBDAT1 DAT_SMB
SRN2K2J-1-GP SMBus address:16
WLAN
ICH_SMBCLK
Minicard
SMB_CLK
Charger
SCL
SMB_DATA
+3.3V_ALW
SDA
SMBus address:12
2N7002DW-7F-GP
ICH_SMBDATA
SRN4K7J-8-GP
GPIO90/AB1E_CLK THRM_SMBCLK
SMBCLK
GPIO91/AB1E_DATA THRM_SMBDAT
SMDATA
+3.3V_ALW
Thermal
B SMBus address:5E
B
SRN8K2J-3-GP
AB1B_CLK/GPIOA4 LCD_SMBCLK
AB1B_DATA/GPIOA2 LCD_SMBDAT
INVERTER
+3.3V_RUN SMBus address:58
LVDS
SRN2K2J-1-GP
I2CC_SCL
LCD_DDCLK
I2CC_SDA LCD_DDCDAT
+5V_RUN
VGA
A A
SRN1K5J-GP
I2CB_SCL
HDMI_SDATA
SCL
I2CB_SDA HDMI_SCLK
SDA HDMI CONN Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Thurman Discrete
Size Document Number Rev
C SMBus Block Diagram -1
Date: Tuesday, November 06, 2007 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1
CLOCK GEN CY28547 INTEL CRESTLINE STRAP PIN PCIE Routing ICH
USB0
USB TABLE
USB1
27M_SS/LCD96_100M SELECTION TABLE LANE1 MiniCard WWAN
BYTE 15
BYTE 10
IO_VOUT[2,1,0] * is Default setting LANE2 MiniCard WLAN
USB1 USB2
Bit2 Bit1 Bit0 IO_VOUT[2,1,0] CFG Strap Low High USB2
Bit5 S1 Bit4 S0 Spread Spectrum S[1:0] IO_VOUT2 IO_VOUT1 IO_VOUT0 LANE3 No use
0 0 -0.5%(Default) 0 0 0 0.3V CFG 5 DMI X 2 DMI X 4 USB3
0
1
1
0
-1.0%
-1.5%
0
0
0
1
1
0
0.4V
0.5V CFG 6 Moby Dick Calistoga
* LANE4 Express Card
USB4 Biometric
1 1 -2.0% 0
1
1
0
1
0
0.6V
0.7V CFG 7 DT/Transportable CPU Mobile CPU
* LANE5 No use
USB5 Camera
D 1
1
0
1
1
0
0.8V(Default)
0.9V CFG 9 Reserved Lane Normal Operation
* LANE6 10/100 LOM
USB6 Express Card
D
1 1 1 1.0V
CFG 10 Reserved Mobility
* USB7 BT
*
PIN34
0 UMA 1 DISC.
CFG 11
CFG 16
Calistoga
* Reserved PCI ROUTING USB8
USB9 MINI Card WWAN
FCTSEL1 FSB Dynamic ODT Disabled Enabled
PIN43 DOT96T 27M_NonSpread CFG 18
* IDSEL INT REQ GNT
PIN44 DOT96C 27M_Spread VCC Select 1.05V 1.5V
PIN47 LCD100/96T SRCT_0 CFG 19
* 1394/
MediaCard
AD17 C
D
1 1
DMI Lane Reserved Normal Operation Reserved Lane
PIN48 LCD100/96C SRCC_0 CFG 20 Only PCIE or SDVO
* PCIE and SDVO
PCIE/SDVO Select
is operation
No SDVO Device
* are operation simu
SDVO Device present
SEL2 SEL1 SEL0 SDVO_CTRLDATA
CPU FSB
present
*
FSC FSB FSA CFG[13:12]
1 0 1 100M X LL Reserved
0 0 1 133M X LH XOR Mode Enabled
C C
0 1 1 166M 667M HL All Z Mode Enabled
0 1 0 200M 800M HH Normal Operation
* INTEL ICH8-M INTEGRATED
INTEL ICH8-M STRAP PIN PULL-UPS and PULL-DOWNS
Signal Usage/When Sampled Comment XOR Chain Entrance Strap
ICH_RSVD
SIGNAL Resistor Type/Value
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 tp3 AZ_DOUT_ICH Description HDA_BIT_CLK PULL-DOWN 20K
PCIE Port Config 1 bit1, pulled low at rising edge of PWROK.When TP3 not 0 0 RSVD
Rising Edge of PWROK pulled low at rising edge of PWROK,sets bit1 of 0 1 Enter XOR Chain HDA_RST# NONE
1 0 Normal Operation(default)
RPC.PC(Config Registers:offset 224h) 1 1 Set PCIE port cofig bit1 HDA_SDIN[3:0] PULL-DOWN 20K
HDA_SYNC PCIE Port Config 1 bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK. HDA_SDOUT PULL-DOWN 20K
GNT2# PCIE Port Config 2 bit0, Sets bit2 of RPC.PC(Config Registers:Offset 224h) HDA_SYNC PULL-DOWN 20K
Rising Edge of PWROK.
GNT[3:0] PULL-UP 20K
GPIO20 Reserved Weak Internal PULL-DOWN.NOTE:This signal should GPIO[20] PULL-DOWN 20K
not be pull HIGH.
LDA[3:0]#/FHW[3:0]# PULL-UP 20K
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
B
GNT3# Top-Block Swap Override. cycles targeting FWH BIOS space). LAN_RXD[2:0] PULL-UP 20K B
Rising Edge of PWROK. Note: Software will not be able to clear the PCI_GNT#3 low = A16 swap override enable
Top-Swap bit until the system is rebooted high = default LDRQ[0] PULL-UP 20K
without GNT3# being pulled down. BOOT BIOS Strap LDRQ[1]/GPIO23 PULL-UP 20K
PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
GNT0# Boot BIOS Destination Controllable via Boot BIOS Destination bit PME# PULL-UP 20K
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). 0 1 SPI
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 0 PCI PWRBTN# PULL-UP 20K
1 1 LPC(Default)
Integrated VccSus1_05 SATALED# PULL-UP 20K
VccSus1_5 and VccCL1_5 Enables integrated VccSus1_05,VccSus1_5 and integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN VRM Enable/Disable.Always VccCL1_5 VRM when sampled high SPI_CS1# PULL-UP 20K
SM_INTVRMEN High=Enable Low=Disable
sampled. SPI_CLK PULL-UP 20K
integrated VccLan1_05VccCL1_05
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