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1 2 3 4 5 6 7 8
Tonga & Tyler (T2) VER : 3C
01
A A
AC/BATT
CONNECTOR PG 32 DC/DC Thermal
+3V_SRC CPU VR RESET CKT CLOCKS
RUN POWER /FAN CTRL
SW Dothan +5VSUS
PG 36 PG 33 PG 31 PG 16 PG 28
PG 37 (478 Micro-FCPGA)
PG 3,4
BATT CHARGER PG 32
4X100 / 4X133MHZ
LVDS Panel Connector
PG 17
B 333 MHZ DDR Alviso B
On Board DDR
PG 10,12 VGA CRT Control
1257 PCBGA
PG 17
333 MHZ DDR
PG 5,6,7,8,9
DDR-SODIMM
PG 11
DMI interface
USB2.0 (P0-P2) 3 port USB conn
PG 29
33MHz PCI
ODD HDD
(Slave) ATA 66/100 (Master) ATA 66/100
PG 25 PG 25 ICH6-M CARDBUS PCMCIA MINI-PCI
609 BGA PCI1510GVF Conn.
PG 18 PG 19 PG 20
PG 13,14,15 USB2.0 (P3)
C C
AC97
LPC
LAN Interface RJ45 & Magnetic
AUDIO MDC 82562ET
PG 23 PG 24
PG 21,22 PG 20
Audio Tip/Ring
Jacks Connector
PG 20,21 PG 24 SIO(Macallan III)
256 Pins LBGA
PG 26,27
D D
PS/2 X-Bus QUANTA
COMPUTER
Title
Keyboard Touchpad Flash Schematic Block Diagram
PG 27 PG 24 PG 27 Size Document Number Rev
VM7 3C
Date: Thursday, July 14, 2005 Sheet 1 of 45
1 2 3 4 5 6 7 8
A B C D E
Alviso Strapping Signals and Configuration
Page.5 For Dothan A stepping
ICH6-M Integrated Pull-up
and Pull-down Resistors ICH6-M EDS 15825
02
1.5V2
Pin Name Strap Description Configuration
000 = Reserved CPU NB CLOCK
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25],
001 = FSB533 BSEL1BSEL0CFG2CFG1CFG0 FS_C FS_B FS_A
010 = FSB800 GNT[4]#/GPO[48], GNT[5]#/GPO[17],
CFG[2:0] FSB Frequency Select 011-100 = Reversed 100MHZ ICH6 internal 20K pull-ups
101 = FSB400 0 0 1 0 1 1 0 1 GNT[6]#/GPO[16], LAD[3:0]#/FB[3:0]#,
4 110-111 = Reversed 4
CFG[3:4] Reversed 133MHZ LAN_RXD[2:0], LDRQ[1]/GPI[41], PME#,
0 1 0 0 1 0 0 1
LDRQ[0], PWRBTN#, TP[3]
0 = DMI x2 For Dothan B stepping
CFG5 DMI x2 Select 1 = DMI x4 (Default)
0 = DDR II CPU NB CLOCK ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0],
CFG6 DDR I / DDR II 1 = DDR I (Default) BSEL1BSEL0CFG2CFG1CFG0 FS_C FS_B FS_A ACZ_SDOUT, ACZ_SYNC, DPRSTP#/TP[4], ICH6 Internal 20K pull-downs
0 = Prescott 100MHZ DPRSLPVR/TP[1], EE_CS, SPKR
CFG7 CPU Strap 1 = Dothan (Default) 0 1 1 0 1 1 0 1
CFG[8:11] Reversed 133MHZ
0 0 0 0 1 0 0 1 USB[7:0][P,N] ICH6 internal 15K pull-downs
00 = Reserved
01 = XOR mode enabled
XOR/ALL Z test 10 = All Z mode enabled DD[7], SDDREQ ICH6 internal 11.5K pull-downs
CFG[12:13] straps 11 = Normal Operation
CFG[14:15] Reversed
(Default) PCI TABLE LAN_CLK ICH6 internal 100K pull-downs
0 = Dynamic ODT Disabled
CFG16 FSB Dynamic ODT 1 = Dynamic ODT Enabled DEVICE IDSEL IRQ REQ# / GNT#
(Default)
CFG17 Reversed PIRQA#
CPU core VCC 0 = 1.05V (Default)
PCMCIA controller AD17 PIRQC# REQ1#/GNT1# ICH6-M IDE Integrated Series
CFG18 Select 1 = 1.5V Termination Resistors
3 CFG19
CPU VTT Select 0 = 1.05V (Default)
1 = 1.2V MINIPCI SLOT AD19
PIRQB#
PIRQD# REQ3#/GNT3# DD[15:0], DIOW#, DIOR#, DREQ, 3
approximately 33 ohm
CFG20 Reversed DDACK#, IORDY, DA[2:0], DCS1#,
SDVOCRTL SDVO Present 0 = No SDVO device present DCS3#, IDEIRQ
_DATA (Default)
1= SDVO device present
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
ICH6-M Strapping Signals and Configuration Power Name Page# Power Name Page#
+1_5V_LAN P.15 +RTC_PWR3_3V P.26,36,38
Pin Name Strap Description Note
P.3,4,5,6,8,9,13,15,16,
+1_5V_PCIE P.15 +VCCP 28,35,37
0=PCI Express Port Config bit 1(default)
ACZ_SDOUT 1=XOR Chain Entrance Test mode
+1_5VRUN P.4,8,14,15,30,37 +VCCRTC P.13,15,26,28
2 ACZ_SYNC
0=PCI Express Port Config bit 1(default) 2
1=Reserved
+1_5VSUS P.15,20,30,31,35,37 CRTVCC P.17
DPRSLPVR Reserved This Signal should not be pulled high.
+2.5VRUN P.6,8,15,17,37 DCIN+ P.32
EE_CS Reserved This Signal should not be pulled high.
+2.5VSUS P.6,8,9,10,11,12,34,37 DC_IN+ P.32
EE_DOUT Reserved This Signal should not be pulled low.
+3V562ET P.23 PBATT+ P.32,38
This functionality intended for
GNT[5]#/GPO[17]# Boot BIOS Destination Selection debug/testing only. P.17,26,30,32,33,34,35,
+3VLAN P.14,15,20,23,24 PWR_SRC 36,37,38
0="Top block swap" mode "Top block swap" ICH6 inverts A16 for
GNT(6)#/GPO(16)# 1=Normal(default) all cycles targeting FWH BIOS space USBVCC0,USBVCC1,
+3V_SRC P.15,23,36,37 USBVCC2 P.29
This Signal has a weak inernal PU
GPIO[25] 0=Enable Internal Vcc2_5V VRM(default) P.3,17,20,24,26,27,28,30,
during RSMRST# and is disabled within
1=Disable Internal Vcc2_5V VRM +3VALW 31,32,36,38 VHCORE P.4,33
100ms after RSMRST# deasserts.
0=Disable Internal VccSus 1.5V VRM(default) P.3,8,11,12,13,14,15,16,17,
INTVRMEN 1=Enable Internal VccSus 1.5V VRM +3VRUN 18,20,21,22,24,25,26,27,28,
30,31,33,37
LINKALERT# Reserved This Signal requires an external PU P.3,14,15,17,18,19,20,22,
+3VSUS 24,26,28,31,34,35,36
REQ[4:1]# XOR Test Chain Selection
+5VALW P.15,17,36,37,38
1 SATALED# Reserved This Signal should not be pulled low.
+5VRUN
P.15,17,20,21,22,24,25,27,
28,30,33,37
1
0=Normal(default)
SPKR 1=NO Reboot This Signal should not be pulled high. P.15,19,20,28,29,34,35,36,
+5VSUS
TP[3]
0=XOR Chain Entrance Test mode This Signal should not be pulled low
37
QUANTA
1=Normal(default) unless using XOR Chain testing.
+15V P.17,28,36,37 COMPUTER
NOTE: All strap signals are sampled on the rising edge of the Title
+AVDD P.21 Dothan Processor (Host BUS)
ICH6-M's PWROK signal.
Size Document Number Rev
+DC_IN p.32 VM7 2A
Date: Thursday, July 14, 2005 Sheet 2 of 45
A B C D E
1 2 3 4 5 6 7 8
5 HA#[3..31]
HA#[3..31]
HA#3 P4
U4A
A3# D0# A19 HD#0
HD#[0..63]
HD#[0..63] 5
+VCCP 03
HA#4 U4 A25 HD#1 -THERMTRIP 1 2
HA#5
HA#6
V3
A4#
A5#
Dothan D1#
D2# A22 HD#2
HD#3 R60
R3 A6# D3# B21
HA#7 V2 A24 HD#4 56_0402
HA#8 A7# D4# HD#5 IERR#
HA#9
W1
T4
A8# 1 OF 3 D5# B26
A21 HD#6
1 2
A HA#10 A9# D6# HD#7 R71 A
W2 A10# D7# B20
HA#11 Y4 C20 HD#8 56_0402
HA#12 A11# D8# HD#9 CPUPWRGD
Y1 A12# D9# B24 1 2
HA#13 U1 D24 HD#10 +3VRUN +3VALW
HA#14 A13# D10# HD#11 R52
AA3 A14# D11# E24
HA#15 Y3 C26 HD#12 200_0402
HA#16 A15# D12# HD#13
AA2 A16# D13# B23
2
2
HA#17 AF4 E23 HD#14
HA#18 A17# D14# HD#15 R56 R72
AC4 A18# D15# C25
HA#19 AC7 H23 HD#16 1.5K_NC 330_NC
HA#20 A19# D16# HD#17 +VCCP
AC3 A20# D17# G25
HA#21 AD3 L23 HD#18
HA#22 A21# D18# HD#19
1
1
AE4 A22# D19# M26 PROCHOT# 27
1
HA#23 AD2 H24 HD#20
A23# D20#
3
HA#24 AB4 F25 HD#21 R59
HA#25 A24# REQUEST DATA D21# HD#22 56_0402
AC6 A25# D22# G24 2
HA#26 AD5 PHASE PHASE J23 HD#23
A26# D23#
3
HA#27 AE2 SIGNALS SIGNALS M23 HD#24 Q9
HA#28 A27# D24# HD#25 CPU_PROCHOT# Q10 RHU002N06_NC
2
1
AD6 A28# D25# J25 2 1 2
HA#29 AF3 L26 HD#26 3904_NC
HA#30 A29# D26# HD#27 R58
AE1 A30# D27# N24
HA#31 HD#28 330_NC
1
AF1 A31# D28# M25
H26 HD#29
D29# HD#30
D30# N25
K25 HD#31
D31# HD#32
5 HADSTB0# U3 ADSTB0# D32# Y26
AE5 AA24 HD#33
5 HADSTB1# ADSTB1# D33#
T25 HD#34 ITP disable guidelines
D34# HD#35
D35# U23
R2 V23 HD#36 Signal Resistor Value Connect To Resistor Placement
5 HREQ#0 REQ0# D36#
P3 R24 HD#37
5 HREQ#1 REQ1# D37# TDI 150 ohm +/- 5% VCCP Within 2.0" of the CPU
T2 R26 HD#38
B 5 HREQ#2 REQ2# D38# B
P1 R23 HD#39
5 HREQ#3 REQ3# D39# TMS 39 ohm +/- 5% VCCP Within 2.0" of the CPU
T1 AA23 HD#40
5 HREQ#4 REQ4# D40#
U26 HD#41
D41# HD#42 TRST# 680 ohm +/- 5% GND Within 2.0" of the CPU
D42# V24
N2 ERROR U25 HD#43
5 ADS# ADS# D43# TCK 27 ohm +/- 5% GND Within 2.0" of the CPU
SIGNALS V26 HD#44
D44# HD#45
D45# Y23
AA26 HD#46 TDO Open VCCP Within 2.0" of the CPU
IERR# D46# HD#47
A4 IERR# D47# Y25
AB25 HD#48
D48# HD#49
5 HBREQ0# N4 BREQ0# D49# AC23
J3 ARBITRATION AB24 HD#50
5 BPRI# BPRI# D50#
L1 PHASE AC20 HD#51
5 BNR# BNR# D51#
J2 SIGNALS AC22 HD#52 +VCCP +VCCP
5 HLOCK# LOCK# D52#
AC25 HD#53
D53# HD#54
5 HIT# K3 HIT# D54# AD23
K4 SNOOP PHASE AE22 HD#55
5 HITM# HITM# D55#
1
1
1
1
L4 SIGNALS AF23 HD#56
5 DEFER# DEFER# D56#
AD24 HD#57
D57# HD#58 R68 R66 R67 R65
C8 BPM0# D58# AF20
B8 RESPONSE AE21 HD#59 54.9/F_0402 54.9/F_0402 39.2/F_0402 150_0402
BPM1# D59# HD#60
A9 BPM2# PHASE D60# AD21
HD#61
2
2
2
2
C9 BPM3# SIGNALS D61# AF25
M3 AF22 HD#62 TDI
5 HTRDY# TRDY# D62#
H1 AF26 HD#63 TMS
5 RS#0 RS0# D63#
5 RS#1 K1 RS1#
L2 TDO
5 RS#2 RS2#
A20M# C2 C23
13 A20M# A20M# DSTBN0# HDSTBN0# 5
FERR# D3 PC C22
13 FERR# FERR# DSTBP0# HDSTBP0# 5
IGNNE# A3 COMPATIBILITY K24
13 IGNNE# IGNNE# DSTBN1# HDSTBN1# 5
CPUPWRGD E4 SIGNALS L24 CPURST#
C 13 CPUPWRGD PWRGOOD DSTBP1# HDSTBP1# 5 C
SMI# B4 W25
13 SMI# SMI# DSTBN2# HDSTBN2# 5
DSTBP2# W24 HDSTBP2# 5
2 1 TCK A13 AE24
TCK DSTBN3# HDSTBN3# 5
R63 27.4/F_0402 TDO A12 DIAGNOSTIC AE25
TDO DSTBP3# HDSTBP3# 5
TDI C12 & TEST
TMS TDI
C11 TMS SIGNALS
2 1 TRST# B13 D25 +3VSUS
TRST# DINV0# HDBI0# 5
R64 680_0402 T9 PAD A16 J26
ITP_CLK0 DINV1# HDBI1# 5
T6 PAD A15 ITP_CLK1 DINV2# T24 HDBI2# 5
B10 PREQ# DINV3# AD20 HDBI3# 5
1
A10 PRDY#
DBR# A7 M2 R69
31 DBR# DBR# DBSY# DBSY# 5
DRDY# H2 DRDY# 5 150_0402
13 INTR D1 LINT0
D4 EXECUTION
13 NMI LINT1
STPCLK#
2
13 STPCLK# C6 STPCLK# CONTROL BCLK1 B14 HCLK_CPU# 16
CPUSLP# A6 SIGNALS B15 DBR#
5,13 CPUSLP# SLP# BCLK0 HCLK_CPU 16
DPSLP# B7
G1: NC for Dothan and 13 DPSLP# DPSLP#
13 DPRSTP# G1 DPRSTP#
DPRSTP# for Yonah
THERMDA B18 B5 CPUINIT#
28 THERMDA THERMDA INIT# CPUINIT# 13
THERMDC A18
28 THERMDC THERMDC
B11 CPURST#
RESET# CPURST# 5
-THERMTRIP C17
28 -THERMTRIP THERMTRIP# THERMAL DIODE C19
DPWR# DPWR# 5
CPU_PROCHOT# B17 PROCHOT#
Dothan Processor
D D
QUANTA
COMPUTER
Title
Dothan Processor (Host BUS)
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