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5 4 3 2 1
MCP61M-M
Page Index
01-COVER PAGE
02-BLOCK DIAGRAM
D
03-BLOCK DISTRIBUTION D
04-CPU M2-1 HyperTransport
REV:A 05-CPU M2-1 DDR2
PCB:15-V02-010010 06-CPU M2-3 Miscellany
BOM:81-605-V02000 07-CPU M2-4 Power and Ground
REV:B 08-DDR2 DIMM
09-DDR2 Termination
PCB:15-V02-010020
BOM:81-605-V02010 10-MCP61 HT
11-MCP61 PCI-E X16
v.A --> v.B 12-MCP61 PCI-E X1/RGMII/DAC
01.P31.add R386 13-MCP61 PCI
02.P31.change dual SW control from GPIO3 to GPIO7 14-MCP61 SATA/IDE
C
03.P31.add R404 C
15-MCP61 AUDIO/USB/MISC
16-MCP61 PWR/GND
17-MCP61 DECOUPLING/SPI
18-VGA
19-1394(VT6307/VT6308P)
20-LAN AC131/GIGA RTL8110SC
21-PCI-E X16 CONN
22-PCI1/PCI2
23-PCI-E X1/TPM
24-LPC SIO-ITE8716F/FDD
25-PS2/COM/LPT
B B
26-USB
27-AUDIO ALC861/660
28-AUDIO ALC861/660(PANEL)
29-PWR CON/FNT PNL
30-CPU VCORE
31-DC-DC
32-ATTENTION
Signature Date
Designer Vincent 05/02/2006
Layout
A A
Elitegroup Computer Systems
Check Title
COVER PAGE
Approval
Size Document Number Rev
B MCP61M-M B
Date: Wednesday, July 05, 2006 Sheet 1 of 32
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
POWER
D D
SUPPLY VREG
CONNECTOR
128-BIT 400/533/667/800MHZ
M2 SOCKET 940 DDRII SDRAM CONN 0
THERM MONITOR
DDRII SDRAM CONN 1
HT 16X16 1GHZ
PCI EXPRESS
PEX X16
PCI EXPRESS
PEX X1
C PCI 33MHZ C
PCI SLOT 1
NFORCE
MCP61 PCI SLOT 2
692 BGA
HDA
7.1 AUDIO
ATA 133
PRIMARY IDE
X10 USB2
INTEGRATED SATA CONTROLLERS (X2) BACK PANEL CONN
X4 - SATA CONN
USB2 PORTS 0-1
X2/GBIT LAN
B USB2 PORTS / 1394 conn 2-3 B
FLOPPY CONN FRONT PANEL HDR
PS2/KBRD CONN USB2 PORTS 4-5
SIO LPC BUS 33MHZ
PARALLEL CONN USB2 PORTS 6-7
ITE8726
BUF SIO CLK 24MHZ
USB2 PORTS 8-9
LPC HDR
SERIAL CONN
MII/RGMII MII/RGMII
4MB FLASH
A AC131 / RTL8110SC / RTL8211B A
Elitegroup Computer Systems
TPM
Title
BLOCK DIAGRAM
Size Document Number Rev
B
MCP61M-M A
Date: Monday, July 03, 2006 Sheet 2 of 32
5 4 3 2 1
5 4 3 2 1
M2 SOCKET 940
CHANNEL A0 0-63
HT_CPU_TXCLK0 MEMORY_A0_CLK[2:0]
HT_CPU_TXCLK0* MEMORY_A0_CLK[2:0]* DIMM 0
D D
HT_CPU_RXCLK0
HT_CPU_RXCLK0* MEMORY_B0_CLK[2:0]
MEMORY_B0_CLK[2:0]*
HT_CPU_TXCLK1
HT_CPU_TXCLK1*
HT_CPU_RXCLK1 DIMM 1
HT_CPU_RXCLK1* CHANNEL B0 64-127
MEMORY_A1_CLK[2:0]
MEMORY_A1_CLK[2:0]*
CPUCLK_IN* MEMORY_B1_CLK[2:0]
CPUCLK_IN MEMORY_B1_CLK[2:0]*
CLKOUT_200MHZ PE0_REFCLK
C
CLKOUT_200MHZ* PE0_REFCLK* PE0 X16 C
HT_CPU_RXCLK1*
HT_CPU_RXCLK1 PE1_REFCLK
HT_CPU_TXCLK1* PE1_REFCLK* PE1 X1
HT_CPU_TXCLK1
HT_CPU_RXCLK0*
HT_CPU_RXCLK0
HT_CPU_TXCLK0*
HT_CPU_TXCLK0
14MHZ OR 24MHZ*
BUF_SIO
MCP61 SIO
LPC_CLK0
PCI_CLK0 PCI SLOT 1
B PCI_CLK1 B
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN PCI SLOT 2
LPC_CLK1
TPM
HDA_BITCLK HDA FLASH LPC
CODEC HEADER
RTC_XTAL
32.0 KHZ
XTAL_IN RGMII_TXCLK LAN
PHY
A RGMII_RXCLK A
25 MHZ
XTAL_OUT Elitegroup Computer Systems
BUF_25MHZ
Title
CLOCK DISTRIBUTION
Size Document Number Rev
B
MCP61M-M A
Date: Monday, July 03, 2006 Sheet 3 of 32
5 4 3 2 1
8 7 6 5 4 3 2 1
CPU1A
HYPERTRANSPORT
L0_CLKIN_H1 N6 AD5 L0_CLKOUT_H1
L0_CLKIN_H(1) L0_CLKOUT_H(1) L0_CLKOUT_H1 10
L0_CLKIN_L1 P6 AD4 L0_CLKOUT_L1
L0_CLKIN_L(1) L0_CLKOUT_L(1) L0_CLKOUT_L1 10
VLDT_B L0_CLKIN_H0 N3
L0_CLKIN_H(0) L0_CLKOUT_H(0)
AD1 L0_CLKOUT_H0
L0_CLKOUT_H0 10
L0_CLKIN_L0 N2 AC1 L0_CLKOUT_L0
L0_CLKIN_L(0) L0_CLKOUT_L(0) L0_CLKOUT_L0 10
R1 51-04 L0_CTLIN_H1 V4 Y6 L0_CTLOUT_H1
D R2 51-04 L0_CTLIN_L1
L0_CTLIN_H0
V5
L0_CTLIN_H(1)
L0_CTLIN_L(1)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
W6 L0_CTLOUT_L1
L0_CTLOUT_H0
STP1
STP2
CPU1E D
U1 W2 L0_CTLOUT_H0 10 INTERNAL MISC E
L0_CTLIN_L0 L0_CTLIN_H(0) L0_CTLOUT_H(0) L0_CTLOUT_L0
V1 W3 L0_CTLOUT_L0 10 L25 E20
L0_CTLIN_L(0) L0_CTLOUT_L(0) RSVD1 RSVD17
L26 B19
L0_CADIN_H15 L0_CADOUT_H15 RSVD2 RSVD18
U6 Y5 L31
L0_CADIN_L15 L0_CADIN_H(15) L0_CADOUT_H(15) L0_CADOUT_L15 RSVD3
V6 Y4 L30 AL4
L0_CADIN_H14 L0_CADIN_L(15) L0_CADOUT_L(15) L0_CADOUT_H14 RSVD4 RSVD19
T4 AB6 AK4
L0_CADIN_L14 L0_CADIN_H(14) L0_CADOUT_H(14) L0_CADOUT_L14 RSVD20
T5 AA6 W26 AK3
L0_CADIN_H13 L0_CADIN_L(14) L0_CADOUT_L(14) L0_CADOUT_H13 RSVD5 RSVD21
R6 AB5 W25
L0_CADIN_L13 L0_CADIN_H(13) L0_CADOUT_H(13) L0_CADOUT_L13 RSVD6
T6 AB4 AE27
L0_CADIN_H12 L0_CADIN_L(13) L0_CADOUT_L(13) L0_CADOUT_H12 RSVD7
P4 AD6 U24 F2
L0_CADIN_L12 L0_CADIN_H(12) L0_CADOUT_H(12) L0_CADOUT_L12 RSVD8 RSVD22
P5 AC6 V24 F3
L0_CADIN_H11 M4 L0_CADIN_L(12) L0_CADOUT_L(12) AF6 L0_CADOUT_H11 AE28 RSVD9 RSVD23
L0_CADIN_L11 L0_CADIN_H(11) L0_CADOUT_H(11) L0_CADOUT_L11 RSVD10
M5 AE6 G4
L0_CADIN_H10 L0_CADIN_L(11) L0_CADOUT_L(11) L0_CADOUT_H10 RSVD24
L6 AF5 Y31 G3
L0_CADIN_L10 L0_CADIN_H(10) L0_CADOUT_H(10) L0_CADOUT_L10 RSVD11 RSVD25
M6 AF4 Y30 G5
L0_CADIN_H9 L0_CADIN_L(10) L0_CADOUT_L(10) L0_CADOUT_H9 RSVD12 RSVD26
K4 AH6 AG31
L0_CADIN_L9 L0_CADIN_H(9) L0_CADOUT_H(9) L0_CADOUT_L9 RSVD13
K5 AG6 V31 AD25
L0_CADIN_H8 L0_CADIN_L(9) L0_CADOUT_L(9) L0_CADOUT_H8 RSVD14 RSVD27
J6 AH5 W31 AE24
L0_CADIN_L8 L0_CADIN_H(8) L0_CADOUT_H(8) L0_CADOUT_L8 RSVD15 RSVD28
K6 AH4 AF31 AE25
L0_CADIN_L(8) L0_CADOUT_L(8) RSVD16 RSVD29
AJ18
L0_CADIN_H7 L0_CADOUT_H7 RSVD30
U3 Y1 AD18 AJ20
L0_CADIN_L7 U2 L0_CADIN_H(7) L0_CADOUT_H(7) W1 L0_CADOUT_L7 AD19 KEY1 RSVD31 C18
L0_CADIN_H6 L0_CADIN_L(7) L0_CADOUT_L(7) L0_CADOUT_H6 KEY2 RSVD32
R1 AA2 AE7 C20
C L0_CADIN_L6
L0_CADIN_H5
T1
R3
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
AA3
AB1
L0_CADOUT_L6
L0_CADOUT_H5
AE8
H3
KEY3
KEY4
RSVD33
RSVD34
G24
G25
C
L0_CADIN_L5 L0_CADIN_H(5) L0_CADOUT_H(5) L0_CADOUT_L5 KEY5 RSVD35
R2 AA1 H4 H25
L0_CADIN_H4 L0_CADIN_L(5) L0_CADOUT_L(5) L0_CADOUT_H4 KEY6 RSVD36
N1 AC2 H20 V29
L0_CADIN_L4 L0_CADIN_H(4) L0_CADOUT_H(4) L0_CADOUT_L4 KEY7 RSVD37
P1 AC3 H21 W30
L0_CADIN_H3 L0_CADIN_L(4) L0_CADOUT_L(4) L0_CADOUT_H3 KEY8 RSVD38
L1 AE2
L0_CADIN_L3 L0_CADIN_H(3) L0_CADOUT_H(3) L0_CADOUT_L3
M1 AE3
L0_CADIN_H2 L0_CADIN_L(3) L0_CADOUT_L(3) L0_CADOUT_H2 ZIF-940PS-TYC
L3 AF1
L0_CADIN_L2 L0_CADIN_H(2) L0_CADOUT_H(2) L0_CADOUT_L2
L2 AE1
L0_CADIN_H1 L0_CADIN_L(2) L0_CADOUT_L(2) L0_CADOUT_H1
J1 AG2
L0_CADIN_L1 L0_CADIN_H(1) L0_CADOUT_H(1) L0_CADOUT_L1
K1 AG3
L0_CADIN_H0 L0_CADIN_L(1) L0_CADOUT_L(1) L0_CADOUT_H0
J3 AH1
L0_CADIN_L0 L0_CADIN_H(0) L0_CADOUT_H(0) L0_CADOUT_L0 L0_CLKIN_H1
J2 AG1 L0_CLKIN_H1 10
L0_CADIN_L(0) L0_CADOUT_L(0) L0_CLKIN_L1
L0_CLKIN_L1 10
L0_CLKIN_H0
L0_CLKIN_H0 10
L0_CLKIN_L0
L0_CLKIN_L0 10
L0_CTLIN_H0
L0_CTLIN_H0 10
L0_CTLIN_L0
L0_CTLIN_L0 10
B B
L0_CADIN_L[0..15]
L0_CADIN_L[0..15] 10
L0_CADIN_H[0..15]
L0_CADIN_H[0..15] 10
L0_CADOUT_H[0..15]
L0_CADOUT_H[0..15] 10
L0_CADOUT_L[0..15]
L0_CADOUT_L[0..15] 10
A A
Elitegroup Computer Systems
Title
CPU M2-1 HyperTransport
Size Document Number Rev
B
MCP61M-M A
Date: Monday, July 03, 2006 Sheet 4 of 32
8 7 6 5 4 3 2 1
8 7 6
CPU1B
5 4 CPU1C
3 2 1
MEMORY INTERFACE A MEMORY INTERFACE B
MA0_CLK_H[2..0] MA0_CLK_H2 AG21 AE14 MA_DATA63 MB0_CLK_H2 AJ19 AH13 MB_DATA63
8,9 MA0_CLK_H[2..0] MA0_CLK_L2 MA0_CLK_H(2) MA_DATA(63) MA_DATA62 MB0_CLK_L2 MB0_CLK_H(2) MB_DATA(63) MB_DATA62
AG20 AG14 AK19 AL13
MA0_CLK_L[2..0] MA0_CLK_H1 MA0_CLK_L(2) MA_DATA(62) MA_DATA61 MB0_CLK_H1 MB0_CLK_L(2) MB_DATA(62) MB_DATA61
G19 AG16 A18 AL15
8,9 MA0_CLK_L[2..0] MA0_CLK_L1 MA0_CLK_H(1) MA_DATA(61) MA_DATA60 MB0_CLK_L1 MB0_CLK_H(1) MB_DATA(61) MB_DATA60
H19 AD17 A19 AJ15
MA0_CS_L[1..0] MA0_CLK_H0 MA0_CLK_L(1) MA_DATA(60) MA_DATA59 MB0_CLK_H0 MB0_CLK_L(1) MB_DATA(60) MB_DATA59
8,9 MA0_CS_L[1..0]
U27 AD13 U31 AF13
MA0_CLK_L0 MA0_CLK_H(0) MA_DATA(59) MA_DATA58 MB0_CLK_L0 MB0_CLK_H(0) MB_DATA(59) MB_DATA58
U26 AE13 U30 AG13
MA0_ODT0 MA0_CLK_L(0) MA_DATA(58) MA_DATA57 MB0_CLK_L(0) MB_DATA(58) MB_DATA57
8,9 MA0_ODT0
AG15 AL14
MA0_CS_L1 MA_DATA(57) MA_DATA56 MB0_CS_L1 MB_DATA(57) MB_DATA56
AC25 AE16 AE30 AK15
MA0_CS_L0 MA0_CS_L(1) MA_DATA(56) MA_DATA55 MB0_CS_L0 MB0_CS_L(1) MB_DATA(56) MB_DATA55
AA24 AG17 AC31 AL16
D MA0_ODT0
MA0_CS_L(0) MA_DATA(55)
MA_DATA(54)
AE18 MA_DATA54
MA_DATA53 MB0_ODT0
MB0_CS_L(0) MB_DATA(55)
MB_DATA(54)
AL17 MB_DATA54
MB_DATA53
D
AC28 AD21 AD29 AK21
MA0_ODT(0) MA_DATA(53) MA_DATA52 MB0_ODT(0) MB_DATA(53) MB_DATA52
AG22 AL21
MA_DATA(52) MA_DATA51 MB_DATA(52) MB_DATA51
AE20 AE17 AL19 AH15
MA1_CLK_H(2) MA_DATA(51) MA_DATA50 MB1_CLK_H(2) MB_DATA(51) MB_DATA50
AE19 AF17 AL18 AJ16
MA1_CLK_L(2) MA_DATA(50) MA_DATA49 MB1_CLK_L(2) MB_DATA(50) MB_DATA49
G20 AF21 C19 AH19
MA1_CLK_H(1) MA_DATA(49) MA_DATA48 MB1_CLK_H(1) MB_DATA(49) MB_DATA48
G21 AE21 D19 AL20
MA_CAS_L MA1_CLK_L(1) MA_DATA(48) MA_DATA47 MB1_CLK_L(1) MB_DATA(48) MB_DATA47
8,9 MA_CAS_L
V27 AF23 W29 AJ22
MA_WE_L MA1_CLK_H(0) MA_DATA(47) MA_DATA46 MB1_CLK_H(0) MB_DATA(47) MB_DATA46
8,9 MA_WE_L
W27 AE23 W28 AL22
MA_RAS_L MA1_CLK_L(0) MA_DATA(46) MA_DATA45 MB1_CLK_L(0) MB_DATA(46) MB_DATA45
AJ26 AL24
8,9 MA_RAS_L MA_DATA(45) MA_DATA44 MB_DATA(45) MB_DATA44
AD27 AG26 AE29 AK25
MA_BANK[2..0] MA1_CS_L(1) MA_DATA(44) MA_DATA43 MB1_CS_L(1) MB_DATA(44) MB_DATA43
8,9 MA_BANK[2..0]
AA25 AE22 AB31 AJ21
MA1_CS_L(0) MA_DATA(43) AG23 MA_DATA42 MB1_CS_L(0) MB_DATA(43) AH21 MB_DATA42
MA_DATA(42) MA_DATA41 MB_DATA(42) MB_DATA41
AC27 AH25 AD31 AH23
MA_CKE0 MA1_ODT(0) MA_DATA(41) MA_DATA40 MB1_ODT(0) MB_DATA(41) MB_DATA40
AF25 AJ24
8,9 MA_CKE0 MA_DATA(40) MA_DATA39 MB_DATA(40) MB_DATA39
AJ28 AL27
MA_ADD[15..0] MA_CAS_L MA_DATA(39) MA_DATA38 MB_CAS_L MB_DATA(39) MB_DATA38
8,9 MA_ADD[15..0]
AB25 AJ29 AC29 AK27
MA_WE_L MA_CAS_L MA_DATA(38) MA_DATA37 MB_WE_L MB_CAS_L MB_DATA(38) MB_DATA37
AB27 AF29 AC30 AH31
MA_DQS_H[8..0] MA_RAS_L MA_WE_L MA_DATA(37) MA_DATA36 MB_RAS_L MB_WE_L MB_DATA(37) MB_DATA36
8 MA_DQS_H[8..0]
AA26 AE26 AB29 AG30
MA_RAS_L MA_DATA(36) MA_DATA35 MB_RAS_L MB_DATA(36) MB_DATA35
AJ27 AL25
MA_DQS_L[8..0] MA_BANK2 MA_DATA(35) MA_DATA34 MB_BANK2 MB_DATA(35) MB_DATA34
8 MA_DQS_L[8..0]
N25 AH27 N31 AL26
MA_BANK1 MA_BANK(2) MA_DATA(34) MA_DATA33 MB_BANK1 MB_BANK(2) MB_DATA(34) MB_DATA33
Y27 AG29 AA31 AJ30
MA_DM[8..0] MA_BANK0 AA27 MA_BANK(1) MA_DATA(33) AF27 MA_DATA32 MB_BANK0 AA28 MB_BANK(1) MB_DATA(33) AJ31 MB_DATA32
8 MA_DM[8..0] MA_BANK(0) MA_DATA(32) MA_DATA31 MB_BANK(0) MB_DATA(32) MB_DATA31
E29 E31
C 8 MA_DATA[63..0]
MA_DATA[63..0]
MA_CKE0
L27
M25
MA_CKE(1)
MA_DATA(31)
MA_DATA(30)
E28
D27
MA_DATA30
MA_DATA29 MB_CKE0
M31
M29
MB_CKE(1)
MB_DATA(31)
MB_DATA(30)
E30
B27
MB_DATA30
MB_DATA29
C
MA_CHECK[7..0] MA_CKE(0) MA_DATA(29) MA_DATA28 MB_CKE(0) MB_DATA(29) MB_DATA28
8 MA_CHECK[7..0]
C27 A27
MA_ADD15 MA_DATA(28) MA_DATA27 MB_ADD15 MB_DATA(28) MB_DATA27
M27 G26 N28 F29
MA_ADD14 MA_ADD(15) MA_DATA(27) MA_DATA26 MB_ADD14 MB_ADD(15) MB_DATA(27) MB_DATA26
N24 F27 N29 F31
MB0_CLK_H[2..0] MA_ADD13 MA_ADD(14) MA_DATA(26) MA_DATA25 MB_ADD13 MB_ADD(14) MB_DATA(26) MB_DATA25
8,9 MB0_CLK_H[2..0]
AC26 C28 AE31 A29
MA_ADD12 MA_ADD(13) MA_DATA(25) MA_DATA24 MB_ADD12 MB_ADD(13) MB_DATA(25) MB_DATA24
N26 E27 N30 A28
MB0_CLK_L[2..0] MA_ADD11 MA_ADD(12) MA_DATA(24) MA_DATA23 MB_ADD11 MB_ADD(12) MB_DATA(24) MB_DATA23
P25 F25 P29 A25
8,9 MB0_CLK_L[2..0] MA_ADD10 MA_ADD(11) MA_DATA(23) MA_DATA22 MB_ADD10 MB_ADD(11) MB_DATA(23) MB_DATA22
Y25 E25 AA29 A24
MB0_CS_L[1..0] MA_ADD9 MA_ADD(10) MA_DATA(22) MA_DATA21 MB_ADD9 MB_ADD(10) MB_DATA(22) MB_DATA21
N27 E23 P31 C22
8,9 MB0_CS_L[1..0] MA_ADD8 MA_ADD(9) MA_DATA(21) MA_DATA20 MB_ADD8 MB_ADD(9) MB_DATA(21) MB_DATA20
R24 D23 R29 D21
MB0_ODT0 MA_ADD7 MA_ADD(8) MA_DATA(20) MA_DATA19 MB_ADD7 MB_ADD(8) MB_DATA(20) MB_DATA19
8,9 MB0_ODT0
P27 E26 R28 A26
MA_ADD6 MA_ADD(7) MA_DATA(19) MA_DATA18 MB_ADD6 MB_ADD(7) MB_DATA(19) MB_DATA18
R25 C26 R31 B25
MA_ADD5 MA_ADD(6) MA_DATA(18) MA_DATA17 MB_ADD5 MB_ADD(6) MB_DATA(18) MB_DATA17
R26 G23 R30 B23
MA_ADD4 MA_ADD(5) MA_DATA(17) MA_DATA16 MB_ADD4 MB_ADD(5) MB_DATA(17) MB_DATA16
R27 F23 T31 A22
MA_ADD3 MA_ADD(4) MA_DATA(16) MA_DATA15 MB_ADD3 MB_ADD(4) MB_DATA(16) MB_DATA15
T25 E22 T29 B21
MA_ADD2 MA_ADD(3) MA_DATA(15) MA_DATA14 MB_ADD2 MB_ADD(3) MB_DATA(15) MB_DATA14
U25 E21 U29 A20
MA_ADD1 MA_ADD(2) MA_DATA(14) MA_DATA13 MB_ADD1 MB_ADD(2) MB_DATA(14) MB_DATA13
T27 F17 U28 C16
MA_ADD0 MA_ADD(1) MA_DATA(13) MA_DATA12 MB_ADD0 MB_ADD(1) MB_DATA(13) MB_DATA12
W24 G17 AA30 D15
MA_ADD(0) MA_DATA(12) MA_DATA11 MB_ADD(0) MB_DATA(12) MB_DATA11
G22 C21
MA_DQS_H7 MA_DATA(11) MA_DATA10 MB_DQS_H7 MB_DATA(11) MB_DATA10
AD15 F21 AK13 A21
MB_CAS_L MA_DQS_L7 MA_DQS_H(7) MA_DATA(10) MA_DATA9 MB_DQS_L7 MB_DQS_H(7) MB_DATA(10) MB_DATA9
8,9 MB_CAS_L
AE15 G18 AJ13 A17
MB_WE_L MA_DQS_H6 MA_DQS_L(7) MA_DATA(9) MA_DATA8 MB_DQS_H6 MB_DQS_L(7) MB_DATA(9) MB_DATA8
8,9 MB_WE_L
AG18 E17 AK17 A16
MB_RAS_L MA_DQS_L6 MA_DQS_H(6) MA_DATA(8) MA_DATA7 MB_DQS_L6 MB_DQS_H(6) MB_DATA(8) MB_DATA7
AG19 G16 AJ17 B15
8,9 MB_RAS_L MA_DQS_L(6) MA_DATA(7) MB_DQS_L(6) MB_DATA(7)
B 8,9 MB_BANK[2..0]
MB_BANK[2..0]
MA_DQS_H5
MA_DQS_L5
AG24
AG25
MA_DQS_H(5) MA_DATA(6)
E15
G13
MA_DATA6
MA_DATA5
MB_DQS_H5
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