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5 4 3 2 1
Foxconn C51GK8MB
Fab :A
D D
nVIDIA C51G (A01) + MCP51 (A01) Chipset for AMD K8 939 CPU
(Mar./31B/2005)
PAGE CONTENT PAGE CONTENT
1 01. COVER 25 24. IDE / Floppy / PS2
2 02. BLOCK DIAGRAM 26 25. PLT / COM
3 03. RESET MAP 27 26. FAN / HARDWARE MONITOR /VID
4 04. CLOCK DISTRIBUTION 28 27. USB CONNECTORS
C C
5 05. PCI DEVICE / VID TABLE 29 28. FLASH / PWRGD SKT
6 06. Athlon 64-1 Hyper Transport 30 29. PWR CONN / FNT PNL / VBAT
7 07. Athlon 64- 2 DDR -1 31 30. ACPI VREG
8 08. Athlon 64- 2 DDR -2 32 31. CK51 CORE / HT VREGS
9 09. Athlon 64_ 3 MISC 33 32. VRM
10 10. Athlon 64- 4 Power 34 33. TI 1394
11 11. DDR SDRAM DIMM1-2 35 34. LAN 88E1111 RTL8201
12 12. DDR SDRAM DIMM3-4 36 35. Audio ALC655 ALC880 ALC850
13 13. DDR ADD / CTL TERMINATI 37 36. Audio Connector
B
14 133 DDRTerminator 38 37 ACPIW83304 B
15 14. C51G_HT
16 15. C51G_VGA PCI-E
17 16. C51G_POWER
18 17. MCP51_HT PCI
19 18. MCP51_SATA IDE RGMII
20 19. MCP51_AC97 USB
21 20. MCP51_POWER & VGA CONN
22 21. PCI_E X16 Slot
A
23 22. PCI SLOT 1 2 3 A
24 23. SIO IT8712F
LEADTEK RESEARCH INC. ASSUMES NO RESPONSIBILITY FOR ANY ERRORS IN DRAWING THESE SCHEMATICS. FOXCONN PCEG
THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE. Title
Cover
COPYRIGHT 2002 LEADTEK RESEARCH INC. . Size Document Number Rev
C C51GK8MB A
Date: Monday, June 13, 2005 Sheet 1 of 38
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5 4 3 2 1
C51GM02 Block Diagram
K8 CPU
SOCKET 939
DDR Memory CH:A
D DDR SDRAM CONN 0 D
Athlon & Athlon FX & Sempron
DDR SDRAM CONN 2
POWER 60 Amp
SUPPLY 64-BIT 100/133/166/200MHZ
CONNECTOR VREG -> ISL6566 => 3 phase
2*12 = 24 pin
2*2 = 4 pin (12V) DDR Memory CH:B
DDR SDRAM CONN 1
PWRBTN# S I/O PANSWHJ SW
DDR SDRAM CONN 3
HT 16X16 1600GT/S CPU_VLD
=> 800M-HT Link
HT_VLD
PCI EXPRESS Lane * 16 PCI_RESET0*
SB PS_ON# ACPI PS_OUT#
PCI Express X16
NFORCE
CRUSH 51 RGB Output
VGA CONN * 1 SLP_S5*
C SLP_S3* PWRGD_PS C
PCI EXPRESS Lane * 1 468 Ball BGA VRM_EN ATX POWER
PCI Express X1
25mm * 25mm
VRM PWM_GD
HT 8X8 2000GT/S PCI SLOT 1
=> 1G-HT Link
PCI V2.3 / 33MHZ
PCI SLOT 2
1394 header * 1 #2
NFORCE
ATA 133
PRIMARY IDE
MCP51 TSB43AB22A
1394 header * 1 #1
ATA 133
SECONDRY IDE
508 Ball BGA
27mm * 27mm AC97 /HDA
AC97 / ALC655 (5.1 Audio) => Default
B or B
Azalia / ALC880 (7.1 Audio)
INTEGRATED SATA
SATA-II CONN * 4
BACK PANEL CONN => 4 Port
X8 USB ( V2.0 EHCI / V1.1 OHCI ) USB2 PORTS 7,8
USB2 PORTS 1,6
10/100Mb (Giga-Bit )LAN PHY
FLOPPY CONN
PS2/KB CONN
LPC BUS V1.0 / 33MHZ
FRONT PANEL Header * 2 => 4 Port
SIO
PARALLEL CONN USB2 PORTS 2,3
ITE IT8712F/IX
A A
USB2 PORTS 4,5
SERIAL CONN (COM1) FOXCONN PCEG
RGMII/MII Title
SERIAL Header (COM2) 4MB FLASH Broadcom AC131 Default
( & B5011U co-lay )
Block Diagram
Size Document Number Rev
Custom C51GK8MB A
Date: Monday, June 13, 2005 Sheet 2 of 38
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RESET MAP
D
K8 Socket 939 D
CPU RST*
CPU PWRGD
CRUSH 51
HT_CPU_PWRGD
HT CPU PWRGD
PE_RESET*
HT_CPU_RST*
HT CPU RST*
HT_MCP_PWRGD
HT MCP PWRGD
HT_MCP_RST*
HT MCP RST*
C C
PEX X16
PEX X1
PWR SWTCH
MCP 51
HT_MCP_RST*
HT MCP RST*
PWR CONN PWRBTN* HT_MCP_PWRGD
PWR BUTTON HT MCP PWRGD
B B
SLP_S3* PCIRST_SLOT1*
PS ON SLP S3* PCI RST0*
PCIRST_SLOT2*
PCI RST1*
PWR GOOD POWER_GOOD PWRGD
PCIRST_SLOT3*
PCI RST2*
PCI RST3* PCIRST_IDE*
LPC_RST* LPCRST_FLASH*
PWRGD SB PWRGD_SB PWRGD_SB
LPCRST_SIO*
CIRCUIT
GPIO_AUX* AC_RESET*
SIO FLASH PRI IDE TI1394 PCI SLOT 2 PCI SLOT 1
SEC IDE
A A
LAN_PHY AUDIO_PHY
RESET* RESET*
FOXCONN PCEG
Title
Reset Map C51GK8MB
Size Document Number Rev
Custom A
Date: Monday, June 13, 2005 Sheet 3 of 38
5 4 3 2 1
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K8 939 CPU
D D
HT_CPU_TXCLK0
HT_CPU_TXCLK0*
MEMCLK_L[0,5,7] DIMM 0
HT_CPU_RXCLK0 MEMCLK_H[0,5,7] CHANNEL A1 0-63
HT_CPU_RXCLK0*
MEMCLK_L[2,3]
HT_CPU_TXCLK1 MEMCLK_H[2,3] NC
HT_CPU_TXCLK1*
HT_CPU_RXCLK1 MEMCLK_L[1,4,6] DIMM 1
HT_CPU_RXCLK1* MEMCLK_H[1,4,6] CHANNEL B1 0~63
CPUCLK_IN*
CPUCLK_IN
CRUSH 51
CLKOUT_200MHZ
CLKOUT_200MHZ*
HT_CPU_RXCLK1*
HT_CPU_RXCLK1
PE0_REFCLK PEX X16
PE0_REFCLK*
HT_CPU_TXCLK1*
C HT_CPU_TXCLK1 C
PE1_REFCLK
HT_CPU_RXCLK0* PE1_REFCLK*
HT_CPU_RXCLK0
HT_CPU_TXCLK0* PE2_REFCLK
HT_CPU_TXCLK0 PE2_REFCLK*
HT_MCP_TXCLK0
HT_MCP_TXCLK0*
XTAL_IN
HT_MCP_RXCLK0
HT_MCP_RXCLK0* 27 MHZ (TV OUT ONLY)
XTAL_OUT
CLKIN_25MHZ
CLKIN_200MHZ*
CLKIN_200MHZ
MCP 51
B B
14MHZ OR 24MHZ
MCPCLK_OUT BUF_SIO
MCPCLK_OUT*
SUSCLK SIO
25MHZ_CLKOUT LPC_CLK0 PCI SLOT 1
PCI_CLK0
HT_MCP_RXCLK0* PCI_CLK1
HT_MCP_RXCLK0 PCI_CLK2
PCI_CLK3 PCI SLOT 2
PCI_CLK4
HT_MCP_TXCLK0* PCI_CLK_FB
HT_MCP_TXCLK0
LPC_CLK1
AC_97CLK AC97
32.0 KHZ RTC_XTAL CODEC FLASH LPC
AC_BITCLK HEADER TI1394
XTAL_IN
AZALIA
25 MHZ
BUF_25MHZ CODEC
XTAL_OUT
A A
LAN
PHY
FOXCONN PCEG
Title
Clock Distribution
Size Document Number Rev
C C51GK8MB A
Date: Monday, June 13, 2005 Sheet 4 of 38
5 4 3 2 1
5 4 3 2 1
PCI INTERRUPT/IDSEL MAP
D
CPU VID TABLE D
BACK PANEL PCI BUS# DEVICE# IDSEL PIN PCI SLOT PCI SLOT PCI SLOT PCI SLOT REQ/GNT
VID [4..0] VDD VID [4..0] VDD
SLOT INTA* INTB* INTC* INTD*
0X00000 1.550V 0X10000 1.150V
TI 1394 01 0X06 22 P_INTZ* 1/1
0X00001 1.525V 0X10001 1.125V
PCI 1 01 0X08 23 P_INTW* P_INTX* P_INTY* P_INTZ* 2/2
0X00010 1.500V 0X10010 1.100V
PCI 2 01 0X09 24 P_INTX* P_INTY* P_INTZ* P_INTW* 3/3
0X00011 1.475V 0X10011 1.075V
0X00100 1.450V 0X10100 1.050V
0X00101 1.425V 0X10101 1.025V
0X00110 1.400V 0X10110 1.000V
0X00111 1.375V 0X10111 0.975V
0X01000 1.350V 0X11000 0.950V
0X01001 1.325V 0X11001 0.925V
0X01010 1.300V 0X11010 0.900V
0X01011 1.275V 0X11011 0.875V
0X01100 1.250V 0X11100 0.850V PCI DEVICE MAP
0X01101 1.225V 0X11101 0.825V
0X01110 1.200V 0X11110 0.800V
DEVICE PCI BUS# DEVICE# FUNCTION DEVICE ID SOT23 SOT23-5/SC70
MCP51 LOGICAL SOT89-5
C
0X01111 1.175V 0X11111 OFF MCP 51 PCI BUS 0 0X01-0X0F -- --
C
MAC /MAC 0 XA 0 0X56/57 3 5 4
PCI-PCI BRIDGE 0 X9 0 0X005C
SATA1 0 X8 0 0X0055
SMBUS ADDRESS MAP SATA0 0 X8 0 0X0054
IDE 0 X6 0 0X0053
DEVICE SMBUS # ADDRESS MODEM CODEC 0 X4 1 0X0058
1 2
DIMM 0 0 1010 000 = 0X50
AUDIO CODEC 0 X4 0 0X0059 1 2 3
USB 2.0 0 X2 1 0X005B
DIMM 1 0 1010 001 = 0X51
USB 1.1 0 X2 0 0X005A
DIMM 2 0 1010 010 = 0X52
SHAPE TRIM 0 X1 2 0X005F
DIMM 3 0 1010 011 = 0X53
LDT 0 X0 0 0X005E
SIO 1 0101 101 = 0X2D
SMBUS2 0 X1 1 0X0052 SOT23-6
PCI SLOT 1 1 ARP SOT223
LEGACY SLAVE 0 ? ? 0X00D3
PCI SLOT 2 1 ARP
TI 1394 1 ARP
LPC 0 X1 0 0X0050/51 6 5 4 4
LOGICAL PCI BUS 1 ? ? ?
A ? PCI SLOT 1
DDC BUS
B ? PCI SLOT 2
DDC BUS
PCI SLOT 3
B PCI SLOT 4 B
PCI SLOT 5 1 2 3
1 2 3
A A
FOXCONN PCEG
Title
PCI Device / VID Table
Size Document Number Rev
C C51GK8MB A
Date: Monday, June 13, 2005 Sheet 5 of 38
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5 4 3 2 1
+1.2V_HT
D D
C183 C190 C179
* 0.22uF
* 0.22uF
* 0.22uF
U16A
C0603 C0603 C0603
DUMMY DUMMY DUMMY C247
SEC 1 OF 6 4.7uF
*
10V, X7R, +/-10% C1206 10V, Y5V, +80%/-20%
E2 V_HT AG4
V_HT
10V, X7R, +/-10% 10V, X7R, +/-10% E1 V_HT AG3
V_HT
F1 V_HT AG2
V_HT
F2 V_HT AG1
V_HT
HTCPU_UP[15..0] HTCPU_DWN[15..0]
14 HTCPU_UP[15..0] HTCPU_DWN[15..0] 14
HTCPU_UP15 R5 HT_RXD<15> V4
HT_TXD<15> HTCPU_DWN15
HTCPU_UP14 P3 HT_RXD<14> Y5
HT_TXD<14> HTCPU_DWN14
HTCPU_UP13 N5 HT_RXD<13> Y4
HT_TXD<13> HTCPU_DWN13
HTCPU_UP12 M3 HT_RXD<12> AB5
HT_TXD<12> HTCPU_DWN12
HTCPU_UP11 K3 HT_RXD<11> AD5
HT_TXD<11> HTCPU_DWN11
HTCPU_UP10 J5 HT_RXD<10> AD4
HT_TXD<10> HTCPU_DWN10
HTCPU_UP9 H3 HT_RXD<9> AF5
HT_TXD<9> HTCPU_DWN9
C C
HTCPU_UP8 G5 HT_RXD<8> AF4
HT_TXD<8> HTCPU_DWN8
HTCPU_UP7 R3 HT_RXD<7> V1
HT_TXD<7> HTCPU_DWN7
HTCPU_UP6 N1 HT_RXD<6> W2
HT_TXD<6> HTCPU_DWN6
HTCPU_UP5 N3 HT_RXD<5> Y1
HT_TXD<5> HTCPU_DWN5
HTCPU_UP4 L1 HT_RXD<4> AA2
HT_TXD<4> HTCPU_DWN4
HTCPU_UP3 J1 HT_RXD<3> AC2
HT_TXD<3> HTCPU_DWN3
HTCPU_UP2 J3 HT_RXD<2> AD1
HT_TXD<2> HTCPU_DWN2
HTCPU_UP1 G1 HT_RXD<1> AE2
HT_TXD<1> HTCPU_DWN1 Retention Module for CPU
HTCPU_UP0 G3 HT_RXD<0> AF1
HT_TXD<0> HTCPU_DWN0
814-PS21BA
HTCPU_DWN*[15..0]
HTCPU_DWN*[15..0] 14
HTCPU_UP*[15..0]
14 HTCPU_UP*[15..0] HTCPU_UP*15 HTCPU_DWN*15
T5 HT_RXD<15>* V3
HT_TXD<15>*
HTCPU_UP*14 P4 HT_RXD<14>* W5
HT_TXD<14>* HTCPU_DWN*14
HTCPU_UP*13 P5 HT_RXD<13>* Y3
HT_TXD<13>* HTCPU_DWN*13
HTCPU_UP*12 M4 HT_RXD<12>* AA5
HT_TXD<12>* HTCPU_DWN*12
HTCPU_UP*11 K4 HT_RXD<11>* AC5
HT_TXD<11>* HTCPU_DWN*11
HTCPU_UP*10 K5 HT_RXD<10>* AD3
HT_TXD<10>* HTCPU_DWN*10
HTCPU_UP*9 H4 HT_RXD<9>* AE5
HT_TXD<9>* HTCPU_DWN*9
HTCPU_UP*8 H5 HT_RXD<8>* AF3
HT_TXD<8>* HTCPU_DWN*8
HTCPU_UP*7 R2 HT_RXD<7>* U1
HT_TXD<7>* HTCPU_DWN*7
HTCPU_UP*6 P1 HT_RXD<6>* W3
HT_TXD<6>* HTCPU_DWN*6
HTCPU_UP*5 N2 HT_RXD<5>* W1
HT_TXD<5>* HTCPU_DWN*5
B HTCPU_UP*4 M1 HT_RXD<4>* AA3
HT_TXD<4>* HTCPU_DWN*4 B
HTCPU_UP*3 K1 HT_RXD<3>* AC3
HT_TXD<3>* HTCPU_DWN*3
HTCPU_UP*2 J2 HT_RXD<2>* AC1
HT_TXD<2>* HTCPU_DWN*2
HTCPU_UP*1 H1 HT_RXD<1>* AE3
HT_TXD<1>* HTCPU_DWN*1
HTCPU_UP*0 G2 HT_RXD<0>* AE1
HT_TXD<0>* HTCPU_DWN*0
HTCPU_UPCLK0 L3 AB1 HTCPU_DWNCLK0
HT_RXCLK<0> HT_TXCLK<0> HTCPU_DWNCLK0 14
14 HTCPU_UPCLK0 HTCPU_UPCLK0* HTCPU_DWNCLK0*
14 HTCPU_UPCLK0* L2 HT_RXCLK<0>* AA1
HT_TXCLK<0>* HTCPU_DWNCLK0* 14
HTCPU_UPCLK1 L5 AB4 HTCPU_DWNCLK1
14 HTCPU_UPCLK1 HT_RXCLK<1> HT_TXCLK<1> HTCPU_DWNCLK1 14
HTCPU_UPCLK1* M5 AB3 HTCPU_DWNCLK1*
HT_RXCLK<1>* HT_TXCLK<1>* HTCPU_DWNCLK1* 14
14 HTCPU_UPCLK1*
HTCPU_UPCNTL R1 U2 HTCPU_DWNCNTL
14 HTCPU_UPCNTL HT_RXCTL HT_TXCTL HTCPU_DWNCNTL 14
HTCPU_UPCNTL* T1 U3 HTCPU_DWNCNTL*
14 HTCPU_UPCNTL* HT_RXCTL* HT_TXCTL* HTCPU_DWNCNTL* 14
A A
FOXCONN PCEG
Title
Athlon 64-1 HyperTransport
Size Document Number Rev
B C51GK8MB A
Date: Wednesday, July 20, 2005 Sheet 6 of 38
5 4 3 2 1
5 4 3 2 1
U16C
SOCKET_939
SEC 3 OF 6
MEM_DATA[63..0] MEM_ECC[7..0]
11,12,39 MEM_DATA[63..0] MEM_ECC[7..0] 11,12,39
MEM_DATA63 AE16 MEMDATA<63> MEMCHECK<7>Y29 MEM_ECC7
MEM_DATA62 AG17 MEMDATA<62> MEMCHECK<6>W27 MEM_ECC6
MEM_DATA61 AG18 MEMDATA<61> MEMCHECK<5>P27 MEM_ECC5
D MEM_DATA60 AE18 MEMDATA<60> MEMCHECK<4>R25 MEM_ECC4 D
MEM_DATA59 AJ16 MEMDATA<59> MEMCHECK<3>W26 MEM_ECC3
MEM_DATA58 AG16 MEMDATA<58> MEMCHECK<2>V25 MEM_ECC2
MEM_DATA57 AE17 MEMDATA<57> MEMCHECK<1>R28 MEM_ECC1
MEM_DATA56 AJ18 MEMDATA<56> MEMCHECK<0>P29 MEM_ECC0
MEM_DATA55 AJ20 MEMDATA<55>
MEM_DATA54 AE20 MEMDATA<54> MEM_DM#[8..0]
MEM_DM#[8..0] 11,12,39
MEM_DATA53 AE23 MEMDATA<53> MEMDM<8>*V29 MEM_DM#8
MEM_DATA52 AG24 MEMDATA<52> MEMDM<7>*AF17 MEM_DM#7
MEM_DATA51 AG19 MEMDATA<51> MEMDM<6>*AG21 MEM_DM#6
MEM_DATA50 AE19 MEMDATA<50> MEMDM<5>*AH27 MEM_DM#5
MEM_DATA49 AJ24 MEMDATA<49> MEMDM<4>*AA25 MEM_DM#4
MEM_DATA48 AE24 MEMDATA<48> MEMDM<3>*L26 MEM_DM#3
MEM_DATA47 AG25 MEMDATA<47> MEMDM<2>*F27 MEM_DM#2
MEM_DATA46 AE25 MEMDATA<46> MEMDM<1>*G20 MEM_DM#1
MEM_DATA45 AD25 MEMDATA<45> MEMDM<0>*E17 MEM_DM#0
MEM_DATA44 AC25 MEMDATA<44>
MEM_DATA43 AF25 MEMDATA<43> MEM_DQS[8..0]
MEM_DQS[8..0] 11,12,39
MEM_DATA42 AJ26 MEMDATA<42> MEMDQS<8>U26 MEM_DQS8
MEM_DATA41 AE27 MEMDATA<41> MEMDQS<7>AH17 MEM_DQS7
MEM_DATA40 AD29 MEMDATA<40> MEMDQS<6>AG20 MEM_DQS6
MEM_DATA39 AB25 MEMDATA<39> MEMDQS<5>AG26 MEM_DQS5
MEM_DATA38 AB27 MEMDATA<38> MEMDQS<4>AA26 MEM_DQS4
MEM_DATA37 AA28 MEMDATA<37> MEMDQS<3>L25 MEM_DQS3
MEM_DATA36 Y25 MEMDATA<36> MEMDQS<2>E27 MEM_DQS2
MEM_DATA35 AC26 MEMDATA<35> MEMDQS<1>E20 MEM_DQS1
MEM_DATA34 AB29 MEMDATA<34> MEMDQS<0>F17 MEM_DQS0
C MEM_DATA33 AA27 MEMDATA<33> C
MEM_DATA32 Y27 MEMDATA<32>
MEM_DATA31 N25 MEMDATA<31> MEMCLK2_L<0>T27 MEM_A2_CLK0 MEM_A2_CLK0 12,38
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