Service Manuals, User Guides, Schematic Diagrams or docs for : Gigabyte GIGABYTE 8AENXP-D - REV 1.01
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5 4 3 2 1
Model Name: 8AENXP-D Revision 1.01
SHEET TITLE SHEET TITLE
01 COVER SHEET 28 IDE
D
02 BLOCK DIAGRAM 29 KB_PS2,GAME PORT D
03 BOM & PCB MODIFY HISTORY 30 FRONT PANEL
04 P4_LGA775_A 31 FRONT USB CONNECTOR
05 P4_LGA775_B 32 CPU_FAN & SYS_FAN
06 P4_LGA775_C 33 AZALIA CODEC ALC880
07 P4_LGA775_D 34 AUDIO JACK 1
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08 GMCH-GRANTSDALE_HOST 35 AUDIO JACK 2
09 GMCH-GARNTSDALE_DDR 36 MARVELL 88E8001 LAN
C C
10 GMCH-GRANTSDALE_PCI E, DMI 37 DISCRETE POWER
11 GMCH-GRANTSDALE_INT VGA 38 CYPRESS USB HUB
12 GMCH-GRANTSDALE_GND 39 ITE 8712GB
13 GMCH-GRANTSDALE_PWR 40 COM_LPT
14 DDRII CHANNEL A 1,2 41 BROADCOM BCM5751 LAN
15 DDRII CHANNEL A 3 42 SILICON IMAGE SIL3114
16 DDRII CHANNEL B 1,2 43 TI 1394B-1
17 DDRII CHANNEL B 3 44 TI 1394B-2
B B
18 DDRII TERMINATION 45 ATX POWER CONN.
19 PCI EXPRESS*16 SLOT 46 DPS-1
20 ICH6 PCI, USB, DMI, LAN 47 DPS-2
21 ICH6 IDE, GPIO, SATA, CTRL 48 DPS-3
22 ICH6 VCC, GND
23 FWH
24 GB/CK410M CLOCK. Digitally signed by dd
A
25 PCI SLOT 1, 2,3 DN: cn=dd, o=dd, ou=dd, A
[email protected], c=US
26 PCI EXPRESS*1 SLOT 1,2,3 Date: 2009.10.23Confidential
Intel 06:55:25
27 H/W MONITOR +07'00'
Title
Cover Sheet
Size Document Number Rev
Custom 8AENXP-D 1.01
Date: Wednesday, November 24, 2004 Sheet 1 of 48
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
INTEL Pentium4
LGA775
D
CLOCK GENERATOR D
VID0~4
DPS
VCORE = 1.4V
VCC3 PAGE 4, 5, 6,7 VCORE = 1.40V (2.8GHz)
CKVDD = 3.3V PAGE 24 5VSB,-12V,+12V,VCC,VCC3,3VDUAL
PAGE 46,47,48
CHANNEL A
DDRII SDRAM DIMM X 3
GAD0~31 MCH 1.8VSTR = 1.8V(MEMORY,SUSPEND POWER)
ADSTB0,ADSTB0- ALDERWOOD MAA0~14 VTT_DDR = 0.9V
PAGE 14,15
ADSTB1,ADSTB1- MAA_CPC1~5
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SBA0~7 MAB_CPC1~5
PCI EXPRESS X16 SBSTB,SBSTB- MDD0~63 CHANNEL B
VDDQ = 1.5V (AGP POWER 4X) GCBE0~3-
-DQSD0~7
DM0~7
DDRII SDRAM DIMM X 3
VCC3 = 3.3V
+12V = 12V ST0~2 AGP BUS
3VDUAL = 3.3V 1.8VSTR = 1.8V(MEMORY,SUSPEND POWER)
VCC = 5V PAGE 19 VCORE = 1.75V / SLEEP : 1.3V VTT_DDR = 0.9V
2_5VSTR = 2.5V(MEMORY) PAGE 16,17
VDDQ = 1.5V (AGP POWER 4X, HUBLINK) PAGE 8 ,9,10,11,12,13
C C
HL0~10
HUB LINK
PCI EXPRESS X1 SLOT CONTROL BUS
1,2,3
VDDQ = 1.5V (AGP POWER 4X) IDE Primary
VCC3 = 3.3V
+12V = 12V
3VDUAL = 3.3V
ICH6R
VCC = 5V PAGE 25
VCC = 5V PAGE 28
USB PORTS 0~7 SERIAL ATA
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I)
VCC = 5V 3VDUAL = 3.3V(SUSPEND POWER)
5VSB = 5V VCC3 = 3.3V
5VUSB = 5V PAGE 31,36,41 RTCVDD = 3.3V VCC = 5V PAGE 21
PAGE 20,21,22
PCI BUS
B FWH/HWMO B
CYPRESS USB PORTS
PCI SLOT 1,2
VCC = 5V
+12 = 12V VCC3 = 3V PAGE 27
-12 = -12V
VCC = 5V
VCC3 = 3.3V PAGE 38 VCC3 = 3V
3VDUAL = 3V PAGE 26
LPC BUS
MARVELL 88E8001
AC97/Azalia ALC880 LPC I/O ITE8712GB-IX
+12V = 12V AC97 LINK PAGE 36
VCC3 = 3.3V VCC = 5V
VCC = 5V 5VSB = 5V
AVDD = 5V PAGE 33 VBAT = 3V PAGE 39
SATA 3114
A AUDIO PORTS : FRONT AUDIO PAGE 42 I/O PORTS : A
LIN_ OUT LINE_IN MIC
TELE CD_IN AUX_IN COMA COMB LPT PS2 IR FDD
PAGE 34,35 PAGE 29,40
FRONT PANEL /CPU FAN
VCC = 5V Intel Confidential
5VSB = 5V
+12 = 12V Title
PVCC = 5V PAGE 32 BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 8AENXP-D 1.01
Date: Wednesday, November 24, 2004 Sheet 2 of 48
5 4 3 2 1
5 4 3 2 1
Model Name: 8AENXP-D Circuit or PCB layout change
for next version
Version: 1.01
PAGE Change Item Reason
D 06/10/04 1.Fix Processor Hot Circuit D
Component value change 2.Remove SLBC1,SLBC2
history 3.Change PCI Single Pull High to VCC 2.2K/8P4R
07/08/04 1.0E 1.Fix P4 Extreme CPU
Data Change Item Reason 07/13/04 1.1A 1.Support DDR2-600
01'05'04 1.Remove High Side MoSFET
2.Support VTT_GMCH Over Voltage
2.Change Q45 to SUD50N024-09P
2004/08/02 2.0A 1.Change MCH to B1
3.Rmove MOSFET HSINK
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2.Change PCB to 2.0
4. Approve LAN Power
2004/08/10 2.1A 1.Change MCH to B2
01'08'04 1.Change MOSFET Gate from 0/6 to 1/6
2.Remove EC80,EC35,EC45,EC71,EC70,EC72, 2004/08/17 2.1B 1.Change F_USB to 5VDual
EC74,LEC9,EC61,EC79
C 3.Change U24 to 10HL6-184201-10 ICS 2.Fix Smart Fan C
CK410M
4.Change U17 to 10GL4-15b252-10 3.Change 330U to 470U
2004/09/02 2.2A 1.Change Vcore Choke to 0.6uH
5.Change DU3 to 10TA1-0F8266-10
2.Support Cedar Mill CPU
02'18'04 1.Change GMCH to A2
2004/10/11 1.0A 1.Change to 8AENXP-D 1.0A
2.Change ICH6 to A1
2004/10/22 1.0B 1.Change Green_USB to USB 2.0
3.Change CLOCK GEN. to ICS 954271
2.BOM Change to PVT
4.Remove Onboard DPS
2004/11/08 1.0C 1.Change LBC51 to 10U/8/Y/10V 1.Approve AVDD25 Voltage
5. Add PROCESSOR HOT CIRCUIT
2004/11/17 1.0D 1.Change U19 to ICH6R/B2
04'22'04 1.Change GMCH to B0
2004/11/24 1.0E 1.Remove Turbo 0 Circuit
2.Change ICH6 to B0
B
3.Change On-Lan to Broadcom 5751 B
4.Change PCB to 0.3
05'11'04 1.Change GMCH to B1
2.Chabge ICH6 to B1
2.Change BCM5751 to A1
4.CHange PCB to 1.0
05'17'04 1.Change C256 0.1U to C256 100
05'18'04 1.Remove U77,U78 Socket
2.Add L15,L10
05'20'04 1.0C ECN 1.Remove DQ43
2.Remove DR219
A A
3.Change CU1 to P/N:10HP5-366880-31
4.Add ITE8712F/IX3
5.Remove BU1,PCI_BT,R552 Intel Confidential
Title
BOM & PCB MODIFY HISTORY
05'31'04 1.0C ECN 1.Add DU5 LM324 TI
Size Document Number Rev
Custom 8AENXP-D 1.01
Date: Wednesday, November 24, 2004 Sheet 3 of 48
5 4 3 2 1
5 4 3 2 1
VCORE
VCORE VCORE VCORE
BC6 BC7 BC8 BC9
10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V
+
+
+
+
BC1 BC2 BC3 BC4 EC163 EC164 EC161 EC162
10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V
100U/2V/SPCAP/X P/N:10CL3-201000-11
100U/2V/SPCAP/X P/N:10CL3-201000-11
D 100U/2V/SPCAP/X P/N:10CL3-201000-11 D
100U/2V/SPCAP/X P/N:10CL3-201000-11
U1A
HA[3..16]
8 HA[3..16]
HA3 L5 D2 -HADS Closed to
A03# ADS# -HADS 8
HA4 P6 C2 -BNR
HA5 M5
A04# BNR#
D4 -HIT
-BNR 8 Pin-H1
A05# HIT# -HIT 8
HA6 L4 H4 R1
A06# RSP#
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HA7 M4 G8 -BPRI 49.9/6/1 GTLREF
A07# BPRI# -BPRI 8 VTT_OR
HA8 R4 B2 -DBSY
A08# DBSY# -DBSY 8
HA9 T5 C1 -DRDY
A09# DRDY# -DRDY 8
HA10 U6 E4 -HITM BC11 R2 C3
A10# HITM# -HITM 8
HA11 T4 AB2 -IERR 0.01U/4/X/16V 100/6/1 1U/6/Y/10V
HA12 A11# IERR# -HINIT
U5 A12# INIT# P3 -HINIT 21
HA13 U4 C3 -HLOCK
A13# LOCK# -HLOCK 8
HA14 V5 E3 -HTRDY C2
A14# TRDY# -HTRDY 8
HA15 V4 AD3 33P/4/N/50V
HA16 A15# BINIT# -DEFER
W5 A16# DEFER# G7 -DEFER 8
C N4 F2 -EDRDY C
RSVD EDRDY# -EDRDY 8
P5 RSVD MCERR# AB3
-HREQ0 K4
8 -HREQ0 REQ0#
-HREQ1 J5 U2 CPU_TP1
8 -HREQ1 REQ1# AP0#
-HREQ2 M6 U3 CPU_TP2
8 -HREQ2 REQ2# AP1#
-HREQ3 K6 RN122 62/8P4R
8 -HREQ3 REQ3#
-HREQ4 J6 F3 -BR0 7 8 TESTHI8
8 -HREQ4 REQ4# BR0# -BR0 8 VTT_OL
-HADSTB0 R6 G3 TESTHI8 5 6 TESTHI9
8 -HADSTB0 ADSTB0# TESTHI08
-HPCREQ G5 G4 TESTHI9 3 4 TESTHI10
8 -HPCREQ PCREQ# TESTHI09
HA[17..31] H5 TESTHI10 1 2
8 HA[17..31] TESTHI10
HA17 AB6
HA18 A17#
W6 A18# DP0# J16 CPU_TP3
HA19 C1
Y6 A19# DP1# H15 CPU_TP4
HA20 Y4 H16 CPU_TP5 220P/4/N/25V
HA21 A20# DP2#
AA4 A21# DP3# J17 CPU_TP6
HA22 AD6 R1525 62/6 -IERR
A22# VTT_OL
HA23 AA5 H1 GTLREF
HA24 A23# GTLREF
AB5 A24#
HA25 AC5 G23 -CPURST R6 62/6/X -IERR
A25# RESET# -CPURST 8 VTT_GMCH
HA26 AB4
HA27 A26# -RS0
AF5 A27# RS0# B3 -RS0 8
HA28 AF4 F5 -RS1 C4 R7 62/6 -BR0
A28# RS1# -RS1 8 VTT_OL
HA29 AG6 A3 -RS2 22P/4/N/50V
A29# RS2# -RS2 8
SP-CAP X 4PCS HA30
HA31
AG4
AG5
A30# R8 62/6 -CPURST
A31# VTT_OL
AH4 A32#
AH5 A33#
VCORE AJ5 A34#
AJ6 A35#
AC4 RSVD
AE4 RSVD
B -HADSTB1 B
8 -HADSTB1 AD5
+
+
+
EC2 EC3 EC4 ADSTB1#
100U/2V/SPCAP/X P/N:10CL3-201000-11
100U/2V/SPCAP/X P/N:10CL3-201000-11
100U/2V/SPCAP/X P/N:10CL3-201000-11
LGA775
CR1
CPU RETAINTION/X
VCORE
BC21 BC23 BC20
10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V/X
A A
VCORE
VCORE
BC25 BC26 BC28 BC29
BC30 BC31 10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V/X Intel Confidential
10U/12/X/6.3V/X 10U/12/X/6.3V/X Title
P4_LGA775-A
Size Document Number Rev
Custom 8AENXP-D 1.01
Date: Wednesday, November 24, 2004 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1
D D
U1B
HD[0..15]
8 HD[0..15] HD[32..47] 8
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HD0 B4 G16 HD32
HD1 D00# D32# HD33
C5 D01# D33# E15
HD2 A4 E16 HD34
HD3 D02# D34# HD35
C6 D03# D35# G18
HD4 A5 G17 HD36
HD5 D04# D36# HD37
B6 D05# D37# F17
HD6 B7 F18 HD38
HD7 D06# D38# HD39
A7 D07# D39# E18
HD8 A10 E19 HD40
HD9 D08# D40# HD41
A11 D09# D41# F20
C HD10 B10 E21 HD42 C
HD11 D10# D42# HD43
C11 D11# D43# F21
HD12 D8 G21 HD44
HD13 D12# D44# HD45
B12 D13# D45# E22
HD14 C12 D22 HD46
HD15 D14# D46# HD47
D11 D15# D47# G22
-DBI0 A8 D19 -DBI2
8 -DBI0 DBI0# DBI2# -DBI2 8
STBN0 C8 G20 STBN2
8 STBN0 DSTBN0# DSTBN2# STBN2 8
STBP0 B9 G19 STBP2
8 STBP0 DSTBP0 DSTBP2 STBP2 8
HD[16..31]
8 HD[16..31] HD[48..63] 8
HD16 G9 D20 HD48
HD17 D16# D48# HD49
F8 D17# D49# D17
HD18 F9 A14 HD50
HD19 D18# D50# HD51
E9 D19# D51# C15
HD20 D7 C14 HD52
HD21 D20# D52# HD53
E10 D21# D53# B15
HD22 D10 C18 HD54
HD23 D22# D54# HD55
F11 D23# D55# B16
HD24 F12 A17 HD56
HD25 D24# D56# HD57
D13 D25# D57# B18
HD26 E13 C21 HD58
HD27 D26# D58# HD59
G13 D27# D59# B21
HD28 F14 B19 HD60
HD29 D28# D60# HD61
G14 D29# D61# A19
HD30 F15 A22 HD62
HD31 D30# D62# HD63
G15 D31# D63# B22
-DBI1 G11 C20 -DBI3
8 -DBI1 DBI1# DBI3# -DBI3 8
STBN1 G12 A16 STBN3
8 STBN1 DSTBN1# DSTBN3# STBN3 8
STBP1 E12 C17 STBP3
8 STBP1 DSTBP1 DSTBP3 STBP3 8
B B
LGA775
A A
Intel Confidential
Title
P4_LGA775-C
Size Document Number Rev
Custom 8AENXP-D 1.01
Date: Wednesday, November 24, 2004 Sheet 5 of 48
5 4 3 2 1
5 4 3 2 1
R1563 R1585 60.4/6/1/X COMP5
VCC3 VTT_OL
49.9/6/1/X GTLREF1 R1586 60.4/6/1/X COMP4
VTT_OR
Note: SC678
R1564 C1292 1U/6/Y/10V/X Place outside of CPU socket
VCCA & VCOREPLL 100/6/1/X 1U/6/Y/10V/X
R10 100/6/1 COMP2
define doesn't same as VTT_OL
R1520 R11 100/6/1 COMP3
VTT_GMCH old P4 design kit 249/6/1
L1 R1507 110/6/1 TESTHI0 C5 R14 60.4/6/1 COMP0
VCC3
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