Service Manuals, User Guides, Schematic Diagrams or docs for : Gigabyte GIGABYTE GIGABYTE GA-M55SLI-S4 - REV 1.0
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GIGABYTE GA-M55SLI-S4 Schematics Revision:1.0
SHEET TITLE SHEET TITLE
A
01 COVER SHEET 26 IDE, FDD
02 BOM & PCB MODIFY HISTORY 27 ATX POWER CONNCTOR
03 BLOCK DIAGRAM 28 VCORE POWER
04 M2 CPU Hyper Transport 29 Discrete Power
05 M2 CPU DDR II 30 DDRII Power & Standby Power
06 M2 CPU Control 31 BIOS (LPC ROM & SPI Flash)
07 M2 CPU POWER & GND 32 FRONT PANEL
08 DDRII A0,B0 33 MARVELL 88E1116 GbE Phy
09 DDRII A1,B1 34 TI 1394A
B 10 DDRII TERMINATION 35 NV-SLI Swirch Board
11 CK804 HT 36 COMA , LPT
12 CK804 PCI-EXPRESS 37
13 CK804 PCI, LPC, CLOCK 38
14 CK804 IDE,SATA 39
15 CK804 AC97,USB,MII,GPIO 40
16 CK804 POWER,GND 41
17 PCI EXPRESS X16 SLOT 42
18 PCI EXPRESS X8 SLOT 43
19 PCI EXPRESS X1 SLOT1,2
C
20 PCI 1,2 SLOT
21 CODEC 850/655/658
22 AUDIO JACK, F_AUDIO
23 IT8712KX
24 FAN, H/W Monitor
GIGABYTE Technology
25 KB_MS/FUSEVCC/PS2 Title
Cover Sheet
Size Document Number Rev
Custom
GA-M55SLI-S4 1.0
Date: Wednesday, May 24, 2006 Sheet 1 of 36
5 4 3 2 1
Model Name:GA-M55SLI-S4 1.0 Circuit or PCB layout change for next version
Component value change history Date Change Item Reason
95.03.27_0.1 1'st version pilot-run
Date Change Item Reason 95/04/26 REV:0.2
D 95.03.27_0.1 Rev 0.1 pilot-run BOM D
NB_HS Footprint:BGAHSINK45X45-5 For LPC enable
M55SLI-S3-00-02
Del LPC flash rom
Change RN29 to 220/8P4R For signals level
Add DDR protect
Add R536 to 8.2K ohm
Change R0603 to R0402-2
95/05/22 M55SLI-S3-00-10A
Location: COAXITL change 11NR6-501004-81 to 11NR6-501004-81R
95/05/22 REV:1.0
Change COMA to COM/GE/SC-6mm/RA/1/D
Modify COAXIAL pin 1
Remove R255, change C222 to 2.2n/4
Del VCC15_OV2
Del socket_M2 10SC1-A01940-21
Change F1_1394,F2_1394 to PH/2*5K9/GY/2.54/VA/D
Change PCB to rev:1.0
C C
B B
A A
GIGABYTE Technology
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom GA-M55SLI-S4 1.0
Date: Wednesday, May 24, 2006 Sheet 2 of 36
5 4 3 2 1
1 2 3 4
BLOCK DIAGRAM
A
POWER
SUPPLY VREG
CONNECTOR SOCKET 940
200/266/333/400MHZ
K8 DDRII SDRAM CONN 0
DDRII SDRAM CONN 1
DDRII SDRAM CONN 2
DDRII SDRAM CONN 3
HT 16X16 1GHZ
PEX X16 PCI EXPRESS X16 GRAPHICS
PCI EXPRESS
PEX X1 PCI 33MHZ
PCI SLOT 1
NFORCE
PCI EXPRESS
PEX X1 PCI SLOT 2
CRUSH K804 AC97
AC97
740BGA PCI SLOT 3
ATA 133
B
PRIMARY IDE X10 USB2
SECONDARY IDE
BACK PANEL CONN
RGMII
INTEGRATED SATA USB2 PORTS 5-4
DOUBLE STACK
X4 - SATA CONN
USB2 PORTS 3-2
X2/GBIT LAN
FRONT PANEL HDR
USB2 PORTS 1-0
FLOPPY CONN
PS2/KBRD CONN USB2 PORTS 7-6
SIO LPC BUS 33MHZ
PARALLEL CONN ITE8712 USB2 PORTS 9-8
LPC HDR
SERIAL CONN
SERIAL HDR
C 4MB FLASH
MII/RGMII
GIGABYTE Technology
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom 1.0
GA-M55SLI-S4
Date: Wednesday, May 24, 2006 Sheet 3 of 36
1 2 3 4
L0_CADIN_L[0..15]
L0_CADIN_L[0..15] 11
L0_CADIN_H[0..15]
L0_CADIN_H[0..15] 11 CPU_VDD_RUN = VCORE
L0_CLKIN_L[0..1]
L0_CLKIN_H[0..1]
L0_CLKIN_L[0..1] 11
CPU_VDDA_RUN = VDDA25
L0_CLKIN_H[0..1] 11
L0_CADOUT_L[0..15]
L0_CADOUT_L[0..15] 11
VLDT_RUN = VCC12_HT
A
L0_CADOUT_H[0..15]
L0_CADOUT_H[0..15] 11 CPU_VDDIO_SUS = DDR18V
L0_CLKOUT_L[0..1]
L0_CLKOUT_H[0..1]
L0_CLKOUT_L[0..1]
L0_CLKOUT_H[0..1]
11
11
CPU_VTT_SUS = DDRVTT
VLDT_A = VCC12_HT
VLDT_B = HT12B
SOCKET_M2A
HYPERTRANSPORT
L0_CLKIN_H1 N6 AD5 L0_CLKOUT_H1
L0_CLKIN_L1 L0_CLKIN_H(1) L0_CLKOUT_H(1) L0_CLKOUT_L1
P6 AD4
L0_CLKIN_H0 L0_CLKIN_L(1) L0_CLKOUT_L(1) L0_CLKOUT_H0
N3 AD1
L0_CLKIN_L0 L0_CLKIN_H(0) L0_CLKOUT_H(0) L0_CLKOUT_L0
N2 AC1
L0_CLKIN_L(0) L0_CLKOUT_L(0)
VCC12_HT R1 49.9/4/1 V4 Y6 L0_CTLOUT_H1 1
L0_CTLIN_H(1) L0_CTLOUT_H(1) TP1
R2 49.9/4/1 V5 W6 L0_CTLOUT_L1 1
L0_CTLIN_L(1) L0_CTLOUT_L(1) TP2
L0_CTLIN_H0 U1 W2 L0_CTLOUT_H0
11 L0_CTLIN_H0 L0_CTLIN_H(0) L0_CTLOUT_H(0) L0_CTLOUT_H0 11
L0_CTLIN_L0 V1 W3 L0_CTLOUT_L0
11 L0_CTLIN_L0 L0_CTLIN_L(0) L0_CTLOUT_L(0) L0_CTLOUT_L0 11
L0_CADIN_H15 U6 Y5 L0_CADOUT_H15
L0_CADIN_L15 L0_CADIN_H(15) L0_CADOUT_H(15) L0_CADOUT_L15
V6 Y4
L0_CADIN_H14 L0_CADIN_L(15) L0_CADOUT_L(15) L0_CADOUT_H14
T4 AB6
L0_CADIN_L14 L0_CADIN_H(14) L0_CADOUT_H(14) L0_CADOUT_L14
T5 AA6
L0_CADIN_H13 L0_CADIN_L(14) L0_CADOUT_L(14) L0_CADOUT_H13
R6 AB5
L0_CADIN_L13 L0_CADIN_H(13) L0_CADOUT_H(13) L0_CADOUT_L13
T6 AB4
L0_CADIN_H12 L0_CADIN_L(13) L0_CADOUT_L(13) L0_CADOUT_H12
P4 AD6
L0_CADIN_L12 L0_CADIN_H(12) L0_CADOUT_H(12) L0_CADOUT_L12
P5 AC6
L0_CADIN_H11 L0_CADIN_L(12) L0_CADOUT_L(12) L0_CADOUT_H11
M4 AF6
L0_CADIN_L11 L0_CADIN_H(11) L0_CADOUT_H(11) L0_CADOUT_L11
M5 AE6
L0_CADIN_H10 L0_CADIN_L(11) L0_CADOUT_L(11) L0_CADOUT_H10
L6 AF5
VCORE L0_CADIN_L10 L0_CADIN_H(10) L0_CADOUT_H(10) L0_CADOUT_L10
M6 AF4
L0_CADIN_H9 L0_CADIN_L(10) L0_CADOUT_L(10) L0_CADOUT_H9
K4 AH6
L0_CADIN_L9 L0_CADIN_H(9) L0_CADOUT_H(9) L0_CADOUT_L9
K5 AG6
B L0_CADIN_H8 J6
L0_CADIN_L(9) L0_CADOUT_L(9)
AH5 L0_CADOUT_H8
SC1 SC2 SC3 L0_CADIN_L8 L0_CADIN_H(8) L0_CADOUT_H(8) L0_CADOUT_L8
K6 AH4
L0_CADIN_L(8) L0_CADOUT_L(8)
0.01U/4/Y5V/50V/Z 0.01U/4/Y5V/50V/Z 0.01U/4/Y5V/50V/Z L0_CADIN_H7 U3 Y1 L0_CADOUT_H7
L0_CADIN_L7 L0_CADIN_H(7) L0_CADOUT_H(7) L0_CADOUT_L7
U2 W1
L0_CADIN_H6 L0_CADIN_L(7) L0_CADOUT_L(7) L0_CADOUT_H6
R1 AA2
L0_CADIN_L6 L0_CADIN_H(6) L0_CADOUT_H(6) L0_CADOUT_L6
T1 AA3
L0_CADIN_H5 L0_CADIN_L(6) L0_CADOUT_L(6) L0_CADOUT_H5
R3 AB1
CLOSE CHIPSET & L0_CADIN_L5 R2
L0_CADIN_H(5) L0_CADOUT_H(5)
AA1 L0_CADOUT_L5
CROSSING BOUNDARY L0_CADIN_H4
L0_CADIN_L4
N1
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
AC2 L0_CADOUT_H4
L0_CADOUT_L4
P1 AC3
L0_CADIN_H3 L0_CADIN_L(4) L0_CADOUT_L(4) L0_CADOUT_H3
L1 AE2
L0_CADIN_L3 L0_CADIN_H(3) L0_CADOUT_H(3) L0_CADOUT_L3
M1 AE3
L0_CADIN_H2 L0_CADIN_L(3) L0_CADOUT_L(3) L0_CADOUT_H2
L3 AF1
L0_CADIN_L2 L0_CADIN_H(2) L0_CADOUT_H(2) L0_CADOUT_L2
L2 AE1
L0_CADIN_H1 L0_CADIN_L(2) L0_CADOUT_L(2) L0_CADOUT_H1
J1 AG2
L0_CADIN_L1 L0_CADIN_H(1) L0_CADOUT_H(1) L0_CADOUT_L1
K1 AG3
L0_CADIN_H0 L0_CADIN_L(1) L0_CADOUT_L(1) L0_CADOUT_H0
J3 AH1
L0_CADIN_L0 L0_CADIN_H(0) L0_CADOUT_H(0) L0_CADOUT_L0
J2 AG1
L0_CADIN_L(0) L0_CADOUT_L(0)
CPU-SK/940AM2/S/15u SOCKET_M2
C
K8-940AM2/RM/BP-M/SC/BK/3M/[12KRC-04K807-41R]
GIGABYTE Technology
Title
CPU HYPER TRANSPORT
Size Document Number Rev
Custom
GA-M55SLI-S4 1.0
Date: Wednesday, May 24, 2006 Sheet 4 of 36
1 2 3 4
SOCKET_M2B SOCKET_M2C
MEMORY INTERFACE A MEMORY INTERFACE B
DCLKA2 AG21 AE14 MDA63 DCLKB2 AJ19 AH13 MDB63
A 8,10 DCLKA2 MA0_CLK_H(2) MA_DATA(63) MDA[0..63] 8,9 8,10 DCLKB2 MB0_CLK_H(2) MB_DATA(63) MDB[0..63] 8,9
-DCLKA2 AG20 AG14 MDA62 -DCLKB2 AK19 AL13 MDB62
8,10 -DCLKA2 MA0_CLK_L(2) MA_DATA(62) 8,10 -DCLKB2 MB0_CLK_L(2) MB_DATA(62)
DCLKA1 G19 AG16 MDA61 DCLKB1 A18 AL15 MDB61
8,10 DCLKA1 MA0_CLK_H(1) MA_DATA(61) 8,10 DCLKB1 MB0_CLK_H(1) MB_DATA(61)
-DCLKA1 H19 AD17 MDA60 -DCLKB1 A19 AJ15 MDB60
8,10 -DCLKA1 MA0_CLK_L(1) MA_DATA(60) 8,10 -DCLKB1 MB0_CLK_L(1) MB_DATA(60)
DCLKA0 U27 AD13 MDA59 DCLKB0 U31 AF13 MDB59
8,10 DCLKA0 MA0_CLK_H(0) MA_DATA(59) 8,10 DCLKB0 MB0_CLK_H(0) MB_DATA(59)
-DCLKA0 U26 AE13 MDA58 -DCLKB0 U30 AG13 MDB58
8,10 -DCLKA0 MA0_CLK_L(0) MA_DATA(58) 8,10 -DCLKB0 MB0_CLK_L(0) MB_DATA(58)
AG15 MDA57 AL14 MDB57
MA_DATA(57) MDA56 MB_DATA(57) MDB56
8,10 -CSA1 AC25 AE16 8,10 -CSB1 AE30 AK15
MA0_CS_L(1) MA_DATA(56) MDA55 MB0_CS_L(1) MB_DATA(56) MDB55
8,10 -CSA0 AA24 AG17 8,10 -CSB0 AC31 AL16
MA0_CS_L(0) MA_DATA(55) MDA54 MB0_CS_L(0) MB_DATA(55) MDB54
AE18 AL17
MODT_A0 MA_DATA(54) MDA53 MODT_B0 MB_DATA(54) MDB53
8,10 MODT_A0 AC28 AD21 8,10 MODT_B0 AD29 AK21
MA0_ODT(0) MA_DATA(53) MDA52 MB0_ODT(0) MB_DATA(53) MDB52
AG22 AL21
DCLKA5 MA_DATA(52) MDA51 DCLKB5 MB_DATA(52) MDB51
9,10 DCLKA5 AE20 AE17 9,10 DCLKB5 AL19 AH15
-DCLKA5 MA1_CLK_H(2) MA_DATA(51) MDA50 -DCLKB5 MB1_CLK_H(2) MB_DATA(51) MDB50
9,10 -DCLKA5 AE19 AF17 9,10 -DCLKB5 AL18 AJ16
DCLKA4 MA1_CLK_L(2) MA_DATA(50) MDA49 DCLKB4 MB1_CLK_L(2) MB_DATA(50) MDB49
9,10 DCLKA4 G20 AF21 9,10 DCLKB4 C19 AH19
-DCLKA4 MA1_CLK_H(1) MA_DATA(49) MDA48 -DCLKB4 MB1_CLK_H(1) MB_DATA(49) MDB48
9,10 -DCLKA4 G21 AE21 9,10 -DCLKB4 D19 AL20
DCLKA3 MA1_CLK_L(1) MA_DATA(48) MDA47 DCLKB3 MB1_CLK_L(1) MB_DATA(48) MDB47
9,10 DCLKA3 V27 AF23 9,10 DCLKB3 W29 AJ22
-DCLKA3 MA1_CLK_H(0) MA_DATA(47) MDA46 -DCLKB3 MB1_CLK_H(0) MB_DATA(47) MDB46
9,10 -DCLKA3 W27 AE23 9,10 -DCLKB3 W28 AL22
MA1_CLK_L(0) MA_DATA(46) MDA45 MB1_CLK_L(0) MB_DATA(46) MDB45
AJ26 AL24
MA_DATA(45) MDA44 MB_DATA(45) MDB44
9,10 -CSA3 AD27 AG26 9,10 -CSB3 AE29 AK25
MA1_CS_L(1) MA_DATA(44) MDA43 MB1_CS_L(1) MB_DATA(44) MDB43
9,10 -CSA2 AA25 AE22 9,10 -CSB2 AB31 AJ21
MA1_CS_L(0) MA_DATA(43) MDA42 MB1_CS_L(0) MB_DATA(43) MDB42
AG23 AH21
MODT_A1 MA_DATA(42) MDA41 MODT_B1 MB_DATA(42) MDB41
9,10 MODT_A1 AC27 AH25 9,10 MODT_B1 AD31 AH23
MA1_ODT(0) MA_DATA(41) MDA40 MB1_ODT(0) MB_DATA(41) MDB40
AF25 AJ24
MA_DATA(40) MDA39 MB_DATA(40) MDB39
AJ28 AL27
-SCASA MA_DATA(39) MDA38 -SCASB MB_DATA(39) MDB38
8,9,10 -SCASA AB25 AJ29 8,9,10 -SCASB AC29 AK27
-SWEA MA_CAS_L MA_DATA(38) MDA37 -SWEB MB_CAS_L MB_DATA(38) MDB37
8,9,10 -SWEA AB27 AF29 8,9,10 -SWEB AC30 AH31
-SRASA MA_WE_L MA_DATA(37) MDA36 -SRASB MB_WE_L MB_DATA(37) MDB36
8,9,10 -SRASA AA26 AE26 8,9,10 -SRASB AB29 AG30
MA_RAS_L MA_DATA(36) MDA35 MB_RAS_L MB_DATA(36) MDB35
AJ27 AL25
SBAA2 MA_DATA(35) MDA34 SBAB2 MB_DATA(35) MDB34
8,9,10 SBAA2 N25 AH27 8,9,10 SBAB2 N31 AL26
SBAA1 MA_BANK(2) MA_DATA(34) MDA33 SBAB1 MB_BANK(2) MB_DATA(34) MDB33
8,9,10 SBAA1 Y27 AG29 8,9,10 SBAB1 AA31 AJ30
SBAA0 MA_BANK(1) MA_DATA(33) MDA32 SBAB0 MB_BANK(1) MB_DATA(33) MDB32
8,9,10 SBAA0 AA27 AF27 AA28 AJ31
MA_BANK(0) MA_DATA(32) MDA31 8,9,10 SBAB0 MB_BANK(0) MB_DATA(32) MDB31
E29 E31
CKEA1 MA_DATA(31) MDA30 CKEB1 MB_DATA(31) MDB30
9,10 CKEA1 L27 E28 9,10 CKEB1 M31 E30
CKEA0 MA_CKE(1) MA_DATA(30) MDA29 CKEB0 MB_CKE(1) MB_DATA(30) MDB29
8,10 CKEA0 M25 D27 8,10 CKEB0 M29 B27
MA_CKE(0) MA_DATA(29) MDA28 MB_CKE(0) MB_DATA(29) MDB28
C27 A27
MAAA15 MA_DATA(28) MDA27 MAAB15 MB_DATA(28) MDB27
M27 G26 N28 F29
8,9,10 MAAA[0..15] MAAA14 MA_ADD(15) MA_DATA(27) MDA26 8,9,10 MAAB[0..15] MAAB14 MB_ADD(15) MB_DATA(27) MDB26
N24 F27 N29 F31
MAAA13 MA_ADD(14) MA_DATA(26) MDA25 MAAB13 MB_ADD(14) MB_DATA(26) MDB25
AC26 C28 AE31 A29
B MAAA12 N26
MA_ADD(13) MA_DATA(25)
E27 MDA24 MAAB12 N30
MB_ADD(13) MB_DATA(25)
A28 MDB24
MAAA11 MA_ADD(12) MA_DATA(24) MDA23 MAAB11 MB_ADD(12) MB_DATA(24) MDB23
P25 F25 P29 A25
MAAA10 MA_ADD(11) MA_DATA(23) MDA22 MAAB10 MB_ADD(11) MB_DATA(23) MDB22
Y25 E25 AA29 A24
MAAA9 MA_ADD(10) MA_DATA(22) MDA21 MAAB9 MB_ADD(10) MB_DATA(22) MDB21
N27 E23 P31 C22
MAAA8 MA_ADD(9) MA_DATA(21) MDA20 MAAB8 MB_ADD(9) MB_DATA(21) MDB20
R24 D23 R29 D21
MAAA7 MA_ADD(8) MA_DATA(20) MDA19 MAAB7 MB_ADD(8) MB_DATA(20) MDB19
P27 E26 R28 A26
MAAA6 MA_ADD(7) MA_DATA(19) MDA18 MAAB6 MB_ADD(7) MB_DATA(19) MDB18
R25 C26 R31 B25
MAAA5 MA_ADD(6) MA_DATA(18) MDA17 MAAB5 MB_ADD(6) MB_DATA(18) MDB17
R26 G23 R30 B23
MAAA4 MA_ADD(5) MA_DATA(17) MDA16 MAAB4 MB_ADD(5) MB_DATA(17) MDB16
R27 F23 T31 A22
MAAA3 MA_ADD(4) MA_DATA(16) MDA15 MAAB3 MB_ADD(4) MB_DATA(16) MDB15
T25 E22 T29 B21
MAAA2 MA_ADD(3) MA_DATA(15) MDA14 MAAB2 MB_ADD(3) MB_DATA(15) MDB14
U25 E21 U29 A20
MAAA1 MA_ADD(2) MA_DATA(14) MDA13 MAAB1 MB_ADD(2) MB_DATA(14) MDB13
T27 F17 U28 C16
MAAA0 MA_ADD(1) MA_DATA(13) MDA12 MAAB0 MB_ADD(1) MB_DATA(13) MDB12
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