Service Manuals, User Guides, Schematic Diagrams or docs for : Gigabyte GIGABYTE_-_MOBO_TRAINNING
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Digitally signed by dd
DN: cn=dd, o=dd,
ou=dd,
email=dddd@yahoo.
-SLP_S3 com, c=US DDR400
F_PANEL Date: 2009.12.17 MEM_SMBDATA
-PWRBTSW / PSIN 19:02:31 +07'00'
ITE SPI MEM_SMBDATA
BIOS
-SLP_S3
8716GB/CX
ALC883
+/-DCLK[11;0]
25MHZ LAD[0;3] 27 MHz
-PSOUT
-IO_PSON
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W83303AG CTRL SIGL
THERMTRIP_CPU_L
-ACZ_RST HTMCP_DWNCNTL
OUT
CPU_VL
PCICLK1
-PPCIRST -HTMCP_DWNCNTL VCC12_HT VCC12_HT
PCICLK L0_CADOUT_H/L[15;0]
HT1_VLD
D -1394RST HTMCP_DWNCLK0 HT_12B
PCICLK3
2 VCC3 VCC12 L0_CLKOUT_H/L[1;0]
MEM_VLD -IDERST -HTMCP_DWNCLK0 VTTDDR
PCICLK4 3VDUAL HTMCP_DWN[0;7] 1P2VPLL_PWR 25VSTR
HT1VDD_E -LPCRST L0_CTLOUT_H/L[1;0]
1394CLK
CPUVDD_EN
N -BIOSRST RTCVDD -HTMCP_DWN[0;7]
2P5V_PWR VCORE
-ATX_PSON
LPC33 HTMCP_UPCNTL L0_CADIN_H/L[15;0]
- VCC15_DUAL
LPC24 -HTMCP_UPCNTL
TPMRST
SB_PWOK L0_CLKIN_H/L[1;0] AMD K8
ROMCLK33 HTMCP_UPCLK0
TPMCLK33 CONTROL SIGL MCP51 C51G
-HTMCP_UPCLK0 L0_CTLIN_H/L[1;0]
97CLK14 AD[0;31] AM2
VCC15 HTMCP_UP[0;7] HTTSTOP_L
-HTMCP_UP[0;7] VCC3
VCC12
-HTMCP_RST CPUCLK0_H/L
VCC -HTMCP_PWRGD
See page 20 -CPURST VDDA25
-MII_RST
MCPOUT_25MHZ CPUREF
MCPOUT_200MHZ CPU_PWRGD
-MCPOUT_200MHZ IN
-HT_REQ#
-HT_STOP#
HT_STOP
#
-
MARVELL VGA
PCI_EX16
88E1116
PCI_EX1 SMBDATA
ATX
PWOK CK8_PWOK SMBCLK MCP51
IEEE1394
TSB43AB23
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AMD K8
200 MHz
AM2
HT
www.kythuatvitinh.com HT
HT
200 MHz
C51G
25 MHz
OTHER
GA-M55plus-S3G 200 MHz
PLLS Introduction
HT
200 MHz
HT
HT
MCP51
OTHER
PLLS
25 MHz
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PCIE_RST#
HT_CPU_PWRGD
AMD K8
PCI_EX16 C51G HT_CPU_RST#
AM2
HTMCP_PWRGD
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PCI_EX1
HTMCP_RST#
ATX
SLP_S3#
PS ON
PWRGD PCI SLOT
PWOK
PPCIRST#_SLOT1
PPCIRST#_SLOT2
MCP51
PPCIRST#_SLOT3
PPCIRST#_SLOT4
SB_PWOK
SB_PWOK
CIRCUIT IDERST#
1394RST# LPCRST_SIO# LPCRST_FLASH#
MII_RST# ACZ_RST#
IDE
ITE SPI
8716GB/CX BIOS
IEEE1394 MARVELL ALC
TSB43AB23 88E1116 883
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5VSB5VDUAL 25.00MHZ 32.768KHZ
3VDUAL
3VDUAL
RTCVDD
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-RTCRST
S5_EN
W83303AD
See page 35
-RSMRST
2N7002
nVIDIA
VBAT
ADVANCED ACPI CONTROLLER MCP51
PWRBTSW
SLP_S3
SB_PWOK
5VSB
System
On-Off PSIN
Button PS ON#
-PWRBTSW ATX
PS ON# W83303AD
Power Supply
IT8716
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4 FET
14CPUVDD_EN 5
SB_PWOK SB_PWOK
VCC3 VCC15 VCC15_DUAL Circuit
AM2
19 7 3 2
CPU_VLD
MCP51 MEM_VLD
W83303AG 3VDUAL
5VDUAL
VCC VCC12 VCC FET
18
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VDDA25
20
HT1VDD_EN 22 -RSMRST S5_EN
21 6
S5_EN
-LPCRST
-SLP_S3
VDDA HT1_VLD FET
-PSOUT
Circuit
CIRCUIT 8 11 -SLP_S5
VDDA25_EN
9 -PWRBTSW Power
17 IT8716 GB/CX button
HT 10 -ATX_PSON
VDDA
VREG
-IO_PSON 1
CIRCUIT W83303AG 5VSB
CK8_PWOK 13 PWOK DDR18V ATX power
VCC12_HT 20 DDRVTT
VCC12
VDDA2518 VCC15 12Core Power Planes
2P5V_PWR
VCORE_PWOK
CPUCLK0_H/L
VCORE VCC12_HT
16 24HTMCP_RST# VCC12 VCC12_HT
26 -CPURST
AM2
23HTMCP_PWRGD C51G 25 CPUPWROK VDDA25
DDR18V DDRVTT
2P5V_PWR VCC3
PWM VID
VCORE
15
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K8 Power Sequence
HT1_VLD CPU_VLD
MCP51
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HT1VDD_EN (S-B) CPUVDD_EN
VCC
PWM
VCORE
VCOR_PWOK
CPU
HT1_EN
CIRCUIT TSM104 FET
Dual Dual
VCC12_HT Diode Diode
CIRCUIT
CPU,C51G
VDDA25_EN
VDDA25 CIRCUIT TSM104 CIRCUIT
CPU
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POWER-UP SEQUENCE
LPC_PD#
HT_VLD
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+12V_HT
HTVDD_EN
CPU_VLD
+V_CPU
CPUVDD_EN
CPU_CLK
LPC_CLK
SUSCLK(32KHz)
PWRGD
COREPowerPlanes
SLP_S3#
MEM_VLD
+2.5V_SUS
+1.25V_VTT_SUS
SLP_S5#
PWRGD_SB
25MHz xtal
+5V_DUAL
+3.3V_DUAL
+1.5V_DUAL
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+3.0V_VBAT www.kythuatvitinh.com 8
Power Sequence Timing
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VCC15 MCP51
FET
1.5V
VCC12_HT C51G
FET AM2 CPU
ATX POWER CONNECTOR
1.2.V
VCC3
DUAL VDDA25
FET 2.5.V
AM2 CPU
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DUAL C51G
2P5V_PWR
FET
3.3V C51G MCP51 IT6716F BIOS ALC883 W83303 DDR2 PCI
VCC DUAL PCI/G
VCC12 C51G MCP51 IT8716F ISL6566 W83303 W83320 IEEE1394
FET D7523
2
DUAL
5VDUAL FET DDR18V DDRVTT W83320G DDR2 AM2 CPU
FET
5VSB PCIE_1
MCP51 W83303AG
FET 3VDUAL FET VCC15_DUAL PCIE_16X
W83310DGIEEE1394 LAN/PC
I
5VSB IT8716F W83303AG
+12V
12V GD75232 PCIE_16X PCIE_1X PCI TSM104 SOUND/CQ4
LM358D
R
ATX
+12V 3 phase vcore AM2 CPU
RTCVDD MCP51
BATTERY
BAT
3.3V
+ VBAT IT8716F
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C51 Power Sequencing
CPU VID AMD K8 MEM
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VREG AM2 VREG
HT
HT_CPU_PWRGD HT_CPU_STOP# VREG
C51G
HTMCP_PWRGD HTMCP_RST#
CPU_VLD
HT_VLD
CPU_VDD_EN
HT_VDD_EN
PWRGD
POWER MCP51
SLP_S3# MEM_VLD
SUPPLY
SB_PWOK SLP_S5#
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C51G/MCP51 Power Sequencing Block Diagram
HT_CPU_PWRGD
HT_CPU_RST#
AMD K8
HT_CPU_UP
HT_CPU_DN
CPU_CLK
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AM2
PRSNT#
PERST#
PE_REFCLK# C51G
HT_MCP_PWRGD
HT_STOP#
HT_MCP_RST#
HT_MCP_UP
HT_MCP_DN
CR_REF_CLK
HT_REQ#
HT_VLD
PCIRST#
HT_VDD_EN CPU_VLD
CPU_VDD_EN
MCP51 MEM_VLD
SLP_S3# CK8_PWOK
SLP_S5# SB_PWOK
LPC_PD#
ROM
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Clock Block Diagram
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CPU Power Supply Interface Signals
Signal Voltage Definition Remark
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VCORE (VDD) 1.5V Core power supply
VCC12_HT/HT 1.2V Hyper Transport I/O ring power supplies
12B
(VLDT_A)
VDD25 (VDDA) 2.5V Filtered PLL Supply Voltage
DDR18V(VDDI 1.8V DDR SDRAM I/O ring power supply
O)
DDRVTT (VTT) 0.9V VTT Regulator voltage
CPU_M_VREF VREF DRAM Interface Voltage Reference
(M_VREF)
COREFB_H/L A Differential feedback for VDD Power Supply
(VDD_FB_H/L)
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C51XE Power Supply Interface Signals
Signal Voltage Definition Remark
VCC12 1.6V Core Power Rail ,this power plane is for
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(+1.2V_COR the C51G core
E)
VCC12_HT 1.2V Isolated Hyper Transport power rail
(+1.2V_HT)
2P5V_PWR 2.5V 2.5V Core Power, this voltage is used to
(+2.5V_COR power the core logic of the C51G
E)
1P2VPLL_PW 1.2V +1.2V Voltage, this is a filtered version
R of the +1.2V_ core
(+12V_PLL) voltage.
1P2VPEA_P 1.2V +1.2V Voltage, provides power to the
WR PCI Express integrated into the C51G
(+12V_PEA)
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MCP55P Power Supply Interface Signals
Signal Voltage Definition Remark
RTCVDD 3.3V RTC Power well ,Battery backed-up
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(+3.3V_VBAT) power plane on the onboard Real Time
Clock.
+5V_DUAL 5V Dual System Supply, The +5V_SB
supply powers this rail in low power
status and the +5V supply powers this
rail during normal operation .
+3.3V_DUAL 3.3 V Dual Pad Supply, The +5V_dual
supply powers this rail in low power
status and the +3V supply powers this
rail during normal operation .
VCC15_DUAL 1.6 V Dual Logic Supply, Power plane for the
(+1.2V_DUAL) logic in the MCP51 that remains active
in all system status .
VCC12 (+1.2V) 1.6V VCORE Logic Supply, Power plane for
(+1.2V_HT) the core logic in MCP51 , also
potentially used for Hyper Transport
pad power.
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AMD K8 AM2 Power Sequencing Signals
Signal I/O Definition Remark
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MEM_VLD# I Memory +2.5 V Power Valid
This signal indicates that the DDR DRAM
+1.8 V power plane is valid.
CPUVDD_EN O CPU VDD Enable This signal controls the
voltage regulator controlling the
CPU_VDD power plane.
CPU_VLD# I CPU VDD Power Valid
This signal indicates that the CPU VDD
power plane is valid.
HT1VDD_EN O Hyper Transport Link +1.2V_HT Enable
This signal controls the voltage regulator
controlling the +1.2V_HT power plane.
HT1_VLD# I Hyper Transport Link +1.2 V Power
Valid
This signal indicates that the +1.2V_HT
power plane is valid.
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