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Agilent PN 8791-5
Tips on External Clock Operation with FASS
Product Note




                      Abstract
                      This product note provides helpful
                      tips and examples of external clock
                      operation with the Agilent Technologies
                      8791/10 Frequency Agile Signal
                      Simulator. Examples of successful
                      external clock operation are considered
                      in the context of two real applications:
                      secure communication receiver test
                      and radar target simulation.




                      Figure 1. External clock operation with
                      FASS
Introduction                               However, there are some applications      System Clock Fundamentals
Standard operation of Agilent              where exact timing is critical, partic-   Let's begin by understanding how FASS
Technologies FASS uses an internal         ularly in many radar and secure com-      clocks are distributed. Figure 2 shows
clock of 134.217728 MHz (227 Hz) to        munication simulations where trigger      a block diagram of the system clocks
provide synthesized frequency resolu-      jitter or timing skew between the sim-    where CLK represents the system
tion of 0.125 Hz nominal. This power-      ulator and the D.U.T. may be intolera-    clock, whether internal or external.
of-two timebase was selected to pro-       ble. In such cases, the FASS can be
vide "convenient" frequency resolu-        successfully synchronized to the sys-     When you are using the standard
tion when used with the direct digital     tem under test by using a suitable        INTERNAL system clock, connect the
synthesizer inside FASS. Because the       external clock source. Of course,         134.217728 MHz signal, CLK OUT
direct digital synthesizer uses a bina-    there are certain ramifications of        (134 MHz), from the Agile Upconverter
ry phase accumulator, any timebase         external clock operation that must be     (AUC) to the EXT CLK INPUT of the
other than a power-of-two would            understood before one can proceed         Agile Carrier Synthesizer (ACS).
result in an awkward frequency reso-       without consequence. Some of these
lution.                                    issues concern the range of valid         To use an EXTERNAL user-supplied
                                           clock operation, triggering and syn-      clock, you must input the clock into
The tradeoff here is that the power-       chronization, effect of external clocks   the EXT CLOCK INPUT of ACS. For
of-two timebase--while providing a         on spectral purity, and possible resid-   specified operation, the clock must
convenient frequency increment--has        ual Doppler drift. We will examine        not exceed these conditions:
a non-power-of-ten reciprocal timing       these effects along with two practical
interval. Specifically, the 227 Hz clock   application examples in communica-        

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